Abstract: The invention provides systems and methods for providing real-time personalized health risk assessments and recommended interventions for a user based on a unique analysis of data collected from a user's mobile and/or wearable devices.

Abstract: A color electrophoretic display and a display method thereof are provided. The color electrophoretic display comprises an achromatic color particle and a plurality of chromatic color particles. The display method of the color electrophoretic display comprises turning on a stylus mode, providing an assigned stylus color, sensing a movement of the stylus to output a black trace, and transferring the black trace into a color trace of the assigned stylus color when the stylus movement stops. The black trace is shown when the achromatic color particle and the chromatic color particles move toward a top electrode, and a refresh time of the color of the black trace is smaller than 50 ms. The color of the assigned stylus color and the color of the black trace have brightness difference and at least one of the hue differences and the saturation differences.

Abstract: A method for skin protection by applying a zinc oxide-on-silicate platelet composite (ZnO/NSP composite) is formulated in a cosmetic composition, to the skin of a subject. The ZnO/NSP composite is made of silicate platelet and ZnO particles adsorbed thereon, in which the ZnO particles are created by the dehydration of Zn(OH)2 formed on the silicate platelet. The ZnO particles adhering on the silicate platelet can effectively improve the dispersibility of zinc oxide particles in water, and the average particle size can reach near nanometer size. Moreover, the ZnO/NSP composite exhibits better antimicrobial and UV light-absorbing properties than ZnO itself, and are not toxic or irritating to the skin.

Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Abstract: A touch display apparatus comprises an electrophoretic structure, a protective layer, and at least one touch sensing layer. The protective layer is disposed on the electrophoretic structure and comprises an organic material layer and an inorganic material layer. The inorganic material layer is located between the electrophoretic structure and the organic material layer. The material of the inorganic material layer comprises silicon dioxide (SiO2). The thickness of the inorganic material layer is from 20 nm to 400 nm. The touch sensing layer is disposed on one side of the protective layer.

Abstract: A CEC system, comprising: a first IC, comprising a first pin and an anti-leakage circuit electrically coupled to the first pin; and a second IC, comprising a second pin electrically coupled to the first pin. The first IC or the second IC is configured to provide a CEC function. Thereby software can be used to simulate CEC functions to increase the number of CEC function sets without increasing hardware costs, to increase the application scope of the CEC system.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: A multimedia device comprises a power input interface, a computing circuit and a load circuit. The power input interface is configured to receive an operating voltage. The computing circuit is configured to receive the operating voltage from the power input interface, and configured to output a pulse-width modulation (PWM) signal. The load circuit is configured to receive a test current from the power input interface, receive the PWM signal, and determine a magnitude of the test current according to a duty ratio of the PWM signal. The computing circuit is configured to monitor the variation of the operating voltage while adjusting the duty ratio of the PWM signal step by step. The computing circuit is configured to determine an upper bound of a power consumption of the computing circuit according to the relationship between the operating voltage and the duty ratio of the PWM signal.

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

Abstract: An RF fingerprint signal processing device configured for executing a machine learning algorithm on a plurality of input signals. The RF fingerprint signal processing device includes a receiver-feature determination circuit and a classifying determination circuit. The receiver-feature determination circuit is configured to compute on the plurality of input signals in a neural network. The classifying determination circuit is coupled with the receiver-feature determination circuit, and the classifying determination circuit is configured to send feedback information of a receiver-feature component to the receiver-feature determination circuit. The receiver-feature determination circuit decreases the receiver-feature weight of the neural network. The receiver-feature weight is associated with the receiver-feature component, and the receiver-feature weight which is decreased is applied for computing an output value of the neural network.

Abstract: A system on a chip (SoC) with a Universal Asynchronous Receiver/Transmitter (UART) interface includes a UART interface circuit, a detection circuit, and a control circuit. The UART interface circuit includes: a plurality of UART signal pads for receiving and transmitting signals; and a UART voltage pad for receiving an external operating voltage. The detection circuit is configured to detect the magnitude of the external operating voltage and thereby generate a detection result. The control circuit is configured to determine setting of a supply voltage for the plurality of UART signal pads according to the detection result. The control circuit makes the setting of the supply voltage be compatible with the external operating voltage according to the detection result, wherein the external operating voltage is a lower first voltage or a higher second voltage, and the first lower voltage is equal to an internal device operating voltage of the SoC.

Abstract: An electronic system includes a main chip, a non-volatile storage circuit, and a detector circuit. The main chip is configured to read first time of a clock circuit. The non-volatile storage circuit is coupled to the main chip. The main chip stores the first time into the non-volatile storage circuit. The detector circuit includes a first output terminal. The first output terminal is coupled to the main chip. When a cold boot event occurs, the main chip reads the first time from the non-volatile storage circuit, and determines a reason of the cold boot event according to the first time, a second time of the clock circuit, and a logic value at the first output terminal.

Abstract: A power supply circuit includes a first regulator and a second regulator. The first regulator is configured to generate a first output signal according to an input signal. A voltage value of the first output signal decreases according to the input signal and a first voltage threshold value at a power-off stage. The second regulator is configured to be enabled according to the first output signal to generate a second output signal according to the input signal. A voltage value of the second output signal decreases according to the input signal and a second voltage threshold value at the power-off stage. The second voltage threshold value is greater than the first voltage threshold value.

Abstract: A media streaming device includes a power manager, a stream processor, and a voltage detector. The power manager receives a power signal from the media playback device to supply power to the stream processor. The stream processor provides media stream to the media playback device for playback. The voltage detector is electrically coupled to the stream processor and captures at least a part of the power supply current to the stream processor. The stream processor is configured to determine whether the power supply voltage remains stable. When the supply voltage remains stable, the stream processor operates in a first mode to provide media stream. When the power supply voltage is unstable, the stream processor operates in a second mode to provide media stream, and the power consumption of the stream processor in the second mode is lower than the power consumption in the first mode.

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Abstract: The present invention discloses an AVS scanning method, wherein the AVS scanning method includes the steps of: mounting a system on chip (SoC) on a printed circuit board (PCB), and connecting the SoC to a storage unit; enabling the SoC to read a boot code from the storage unit, and executing the boot code to perform an AVS scanning operation on the SoC to determine a plurality of target supply voltages respectively corresponding to a plurality of operating frequencies of the SoC to establish an AVS look-up table; and storing the AVS look-up table into the SoC or the storage unit.

Abstract: The present invention provides a processor including a core circuit, a plurality of clock signal generation circuits, a multiplexer and a detection circuit is disclosed. The core circuit is supplied by a supply voltage. The plurality of clock signal generation circuits are configured to generate a plurality of clock signals with different frequencies, respectively, wherein a number of the plurality of clock signals is equal to or greater than three. The multiplexer is configured to receive the plurality of clock signals, and to select one of the plurality of clock signals to serve as an output clock signal according to a control signal, wherein the core circuit uses the output clock signal to serve as an operating clock. The detection circuit is configured to detect a level of the supply voltage received by the core circuit in a real-time manner, to generate the control signal.

Abstract: A package substrate and a chip package structure using the same are provided. The package substrate includes a laminated board including first to third wiring layers, a pad array, a plurality of ground conductive structures, and a plurality of power conductive structures. At least one of the ground (or power) conductive structures includes two first ground (or power) conductive posts and a second ground (or power) conductive post. The two first ground (or power) conductive posts and the second ground (or power) conductive post are arranged along a first direction, and the second ground (or power) conductive post is located between two orthographic projections of the two first ground (or power) conductive posts. Each of the ground conductive structures in a first column and each of the power conductive structures in a second column are offset from each other in a second direction.

Abstract: A circuit includes an input impedance, an operational amplifier, a voltage-adjusting circuit, a pulse-generating circuit, and a drive circuit. The input impedance is coupled to an input terminal of the operational amplifier, receives an input voltage, and outputs an input current. The operational amplifier is coupled to a first power voltage and outputs an amplified signal according to an input operating voltage and a feedback signal. The voltage-adjusting circuit adjusts the input operating voltage of the operational amplifier. The pulse-generating circuit generates a pulse width modulation signal according to the amplified signal. The drive circuit is coupled to a second power voltage and generates a driving signal according to the pulse width modulation signal. The feedback signal is correlated with the driving signal.

Abstract: An audio receiver includes a first signal port, a second signal port, a power supply port, a power ground port, and an amplifier circuit. The first signal port is coupled to an audio signal line of a transmission interface. The second signal port is coupled to an audio ground line of the transmission interface. The power supply port is coupled to a power supply line of the transmission interface to generate a power supply level to the power supply line. The power ground port is connected to the ground level and to a power ground line of the transmission interface. When the audio receiver is outputting a power supply current to the audio source device through the power supply port via the power supply line, a connection state between the second signal port and the power ground port is at a high impedance state.