Patents by Inventor Min Liu

Min Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379664
    Abstract: Some embodiments relate to an integrated chip structure. The integrated chip structure includes a substrate having a first device region and a second device region. A plurality of first transistor devices are disposed in the first device region and respectively include epitaxial source/drain regions disposed on opposing sides of a first gate structure. The epitaxial source/drain regions have an epitaxial material. A plurality of second transistor devices are disposed in the second device region and respectively include implanted source/drain regions disposed on opposing sides of a second gate structure. A dummy region includes one or more dummy structures. The one or more dummy structures have dummy epitaxial regions including the epitaxial material.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Yu-Chang Jong, Yi-Huan Chen, Chien-Chih Chou, Tsung-Chieh Tsai, Szu-Hsien Liu, Huan-Chih Yuan, Jhu-Min Song
  • Publication number: 20240376073
    Abstract: The invention provides novel heterocyclic compounds having the general formula (I), and pharmaceutically acceptable salts thereof, wherein R1 to R6 are as described herein: Frther provided are pharmaceutical compositions including the compounds, processes of manufacturing the compounds and methods of using the compounds as medicaments, in particular methods of using the compounds as antibiotics for the treatment or prevention of bacterial infections and resulting diseases.
    Type: Application
    Filed: January 4, 2024
    Publication date: November 14, 2024
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Sandra Marie Joseph GRALL-ULSEMER, Xingchun HAN, Joel Lukas KNECHT, Christian LERNER, Mingming LI, Yongqiang LIU, Patrizio MATTEI, Matthias NETTEKOVEN, Philippe PFLIEGER, Theodor STOLL, Jianhua WANG, Min WANG, Yongguang WANG, Song YANG, Chengang ZHOU
  • Publication number: 20240379535
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Publication number: 20240375042
    Abstract: A packing for gas separation from a liquid absorbent includes a body having a corrugated surface or surface sub-texture adapted to create local turbulence within a liquid absorbent with which the body has been wetted. The body may also has a corrugated profile wherein the surface sub-texture comprises a plurality of individual scallops and the corrugated profile comprises a plurality of individual furrow with between about 2 and about 50 individual scallops per furrow. The packing is useful in a method for gas separation from a liquid absorbent.
    Type: Application
    Filed: May 10, 2024
    Publication date: November 14, 2024
    Inventors: Jesse Thompson, Min Xiao, Kunlei Liu
  • Publication number: 20240376622
    Abstract: A method of recycling solar panels, including a frame, glass, silicon wafers, and wiring, incorporates the steps of: (a) delaminating the solar panel by breaking down ethylene-vinyl acetate polymer in the solar panel to generate fumed acetic acid, (b) dissolving silver from the silicon wafers of the solar panel in a metal recovery solution using the fumed acetic acid generated during the delaminating and (c) recovering the dissolved silver from the metal recovery solution.
    Type: Application
    Filed: May 9, 2024
    Publication date: November 14, 2024
    Inventors: Xin Gao, Min Xiao, Kunlei Liu, Aron Patrick
  • Publication number: 20240380788
    Abstract: Methods and devices for encrypting Network Configuration Protocol (NETCONF) datastore in communication networks are disclosed. One of the methods is performed by a device using NETCONF. The method comprises enabling a function for NETCONF Datastore Security (DS-SEC). The method further comprises publishing a first indication indicating that the device supports the NETCONF DS-SEC function.
    Type: Application
    Filed: August 16, 2021
    Publication date: November 14, 2024
    Inventors: Daiying Liu, Renwang Liu, Min Luo
  • Patent number: 12142560
    Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: November 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Shi Liu, Chien-Hsun Lee, Jiun Yi Wu, Hao-Cheng Hou, Hung-Jen Lin, Jung Wei Cheng, Tsung-Ding Wang, Yu-Min Liang, Li-Wei Chou
  • Publication number: 20240368117
    Abstract: The invention provides novel heterocyclic compounds having the general formula (I), and pharmaceutically acceptable salts thereof, wherein X, D, R1 to R4, and R6 to R10 are as described herein. Further provided are pharmaceutical compositions including the compounds, processes of manufacturing the compounds and methods of using the compounds as medicaments, in particular methods of using the compounds as antibiotics for the treatment or prevention of bacterial infections and resulting diseases.
    Type: Application
    Filed: November 10, 2023
    Publication date: November 7, 2024
    Applicant: Hoffmann-La Roche Inc.
    Inventors: Mathis BRAENDLIN, Sandra Marie Joseph GRALL-ULSEMER, Xingchun HAN, Christian LERNER, Mingming LI, Yongqiang LIU, Sébastien SCHMITT, Jianhua WANG, Yongguang WANG, Min WANG, Song YANG, Chengang ZHOU
  • Publication number: 20240371891
    Abstract: An electronic device includes a substrate, two data lines, two scan lines, an opening region and a light shielding pattern. The two data lines are adjacently disposed on the substrate. The two scan lines are adjacently disposed on the substrate and extend along a first direction. The two data lines and the two scan lines define a pixel. The opening region is disposed corresponding to the pixel and has a first edge and a second edge disposed opposite to each other and extending along the first direction. There is a spaced distance between the first edge and the second edge in a second direction perpendicular to the first direction. The light shielding pattern is disposed adjacent to the opening region and includes a first portion located between a first extending line of the first edge and a second extending line of the second edge.
    Type: Application
    Filed: April 7, 2024
    Publication date: November 7, 2024
    Applicant: InnoLux Corporation
    Inventors: Cheng-Min Wu, Ming-Jhih Chen, Wei-Chen Liu
  • Publication number: 20240371636
    Abstract: A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20240371653
    Abstract: A method for manufacturing a semiconductor device includes depositing a hard mask layer on an upper surface of an insulating layer. The hard mask layer is etched to form an opening in the hard mask layer. A via recess is formed in the insulating layer through the opening. A first photoresist layer is formed on the hard mask layer and in the via recess. The first photoresist layer is etched to form a photoresist plug in the via recess. Two opposite sides of the opening are etched to remove portions of the hard mask layer and thereby a portion of the upper surface of the insulating layer is exposed. The photoresist plug is removed. Metal is deposited in the via recess and on the exposed surface of the insulating layer. The metal is patterned.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Min HSIAO, Chih-Ming LAI, Chien-Wen LAI, Ya Hui CHANG, Ru-Gun LIU
  • Publication number: 20240372551
    Abstract: The application discloses a programmable logic circuit, which comprising: a first lookup table circuit for generating and outputting a first output signal based on a received input signal; a second lookup table circuit for generating a carry propagation signal and a carry generation signal based on a received input signal, selecting one of the signals as the output; a first selection circuit for receiving a carry input signal and a carry generation signal, selecting one of the signals as the output based on the carry propagation signal; a second selection circuit for receiving a first output signal and a second output signal, selecting one of the signals as the output based on the selection output signal. The circuit provided in this application includes the addition operation of multivariate functions, which improves the configuration flexibility and logic resource utilization efficiency of programmable logic devices in addition operation mode.
    Type: Application
    Filed: May 1, 2024
    Publication date: November 7, 2024
    Inventors: CHANGLONG WANG, PEIFU SHEN, KANG YU, BEIBEI LIU, HENG ZHANG, MIN ZHANG, QIPAN FU
  • Patent number: 12136973
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive, from a base station, a channel state information (CSI) configuration indicating a first feedback reporting periodicity for a dominant, or strong, spatial layer and a second feedback reporting periodicity for a non-dominant, or weak, spatial layer. The UE may transmit a first CSI report for at least the dominant spatial layer according to the first feedback reporting periodicity. The UE may transmit a second CSI report for the non-dominant spatial layer according to the second feedback reporting periodicity. In some cases, for aperiodic reporting, the UE may be triggered by downlink control information to report CSI for the dominant spatial layer. In some cases, the CSI configuration may indicate different codebooks for the dominant and non-dominant spatial layers.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: November 5, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Liangming Wu, Yu Zhang, Chenxi Hao, Kangqi Liu, Min Huang, Rui Hu, Hao Xu, Wei Xi
  • Patent number: 12136647
    Abstract: The present invention provides a power device with super junction structure (or referred to as super junction power device) and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Therefore, the process is simple, the cost is low and yield and reliability are high.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: November 5, 2024
    Assignee: SiEn (QingDao) Integrated Circuits Co., Ltd.
    Inventors: Min-Hwa Chi, Conghui Liu, Huan Wang, Longkang Yang, Richard Ru-Gin Chang
  • Publication number: 20240360733
    Abstract: A downhole traction system includes a driving system and a downhole wheeled tractor. The driving system is connected with the downhole wheeled tractor; the downhole wheeled tractor comprises a tractor body, a power unit and a plurality of traction units; the plurality of traction units are arranged along the extension direction of the tractor body; each of the traction units comprises a driving arm, a supporting arm, a supporting wheel, a driving assembly and a supporting assembly; the driving arm and the supporting arm are movably connected with the tractor body; and the supporting wheel is connected with the driving arm and the supporting arm. When the supporting assembly drives the supporting arm to extend along the radial direction of the tractor body under the hydraulic drive action of the hydraulic power unit, the supporting wheel can be abutted against the well wall.
    Type: Application
    Filed: November 14, 2023
    Publication date: October 31, 2024
    Inventors: Jianguo ZHAO, Qingyou LIU, Haiyan ZHU, Min WAN, Guorong WANG, Xuecheng DONG, Xu LUO, Yingju PEI, Xingming WANG
  • Publication number: 20240363443
    Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Wei-Min Liu, Hsueh-Chang Sung, Li-Li Su, Yee-Chia Yeo
  • Publication number: 20240361082
    Abstract: This disclosure relates to a vapor chamber configured to accommodate a cooling fluid. The vapor chamber includes a first cover, a second cover, a first capillary structure, and a second capillary structure. The second cover and the first cover are attached to each other to form a chamber therebetween. The chamber is configured to accommodate the cooling fluid. The first capillary structure is located in the chamber and stacked on the first cover. The second capillary structure is located in the chamber and stacked on the first capillary structure. The second capillary structure is different from the first capillary structure. A projection of the second capillary structure onto the first cover is smaller than a projection of the first capillary structure onto the first cover.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Applicant: VAST GLORY ELECTRONICS & HARDWARE & PLASTIC(HUI ZHOU) LTD.
    Inventors: Lei Lei LIU, Xiao Min ZHANG, Xue Mei WANG
  • Publication number: 20240364460
    Abstract: Systems, methods, non-transitory processor-readable media, and apparatuses for determining, by a wireless communication device, a time-domain resource and a frequency-domain resource for transmitting at least one repetition of a Physical Random Access Channel (PRACH). The wireless communication device transmits to a base station, the at least one repetition of the PRACH using the time-domain resource and the frequency-domain resource.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: ZTE Corporation
    Inventors: Xing LIU, Junfeng ZHANG, Xianghui HAN, Shuaihua KOU, Min REN
  • Patent number: 12129242
    Abstract: The present invention provides novel substituted benzimidazole derivatives used as DAAO inhibitors and for treatment and/or prevention of neurological disorders.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: October 29, 2024
    Assignees: NATIONAL TAIWAN UNIVERSITY, NATIONAL YANG MING CHIAO TUNG UNIVERSITY, NATIONAL HEALTH RESEARCH INSTITUTES
    Inventors: Yufeng Jane Tseng, Yu-Li Liu, Chung-Ming Sun, Wen-Sung Lai, Chih-Min Liu, Hai-Gwo Hwu
  • Patent number: 12130248
    Abstract: A heat source simulation structure includes a heating body and a heating member to form a simulation heat source main body for conducting heat. The simulation heat source main body is enclosed in an outer case and a heating substrate with electrical insulation and heat insulation properties to avoid dissipation of the heat. The heating member is electrically connected with an external power supply for heating the heating body. A thermocouple member is disposed on the heating body corresponding to the heating member. A temperature monitoring port is connected with a data collection meter for recording the temperature of the heating body. By means of the heat insulation design enclosing the simulation heat source main body, the contact thermal resistance between the heating member and the heating body is reduced, further to lower the heat loss of the heat source simulation structure and enhance the measurement precision and reliability.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: October 29, 2024
    Assignee: ASIA VITAL COMPONENTS (CHINA) CO., LTD.
    Inventors: Xiao-Xiang Zhao, Chun-Lin Mao, Han-Min Liu