Patents by Inventor Min Lun Chuang

Min Lun Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7432738
    Abstract: A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 7, 2008
    Assignee: National Tsing Hua University
    Inventors: Chun Yao Wang, Min Lun Chuang
  • Publication number: 20080238480
    Abstract: A reversible sequential apparatus comprises a first logic gate and a second logic gate. The first logic gate includes first, second and third input terminals and first, second and third output terminals. The second logic gate includes first and second input lines and first and second output lines. The first input terminal for carrying a clock signal is coupled to the first output terminal and the second input terminal for carrying an input signal is coupled to the second output terminal. When the first input terminal and the second input terminal are simultaneously set to a first state, the level of the third output terminal is inverse to the level of the third input terminal; otherwise, the level of the third output terminal is identical to the level of the third input terminal. The third output terminal, second input line and second output line are coupled to each other.
    Type: Application
    Filed: March 28, 2007
    Publication date: October 2, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chun Yao Wang, Min Lun Chuang
  • Publication number: 20080238479
    Abstract: A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.
    Type: Application
    Filed: March 19, 2007
    Publication date: October 2, 2008
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Chun Yao Wang, Min Lun Chuang
  • Patent number: 7427876
    Abstract: A reversible sequential element comprises a first logic gate and a second logic gate. The first logic gate includes a first input terminal, a second input terminal, a third input terminal, a first output terminal coupled to the first input terminal, a second output terminal and a third output terminal. The second logic gate includes a first input line, a second input line, a first output line and a second output line. When the first input terminal is set to a first state, the second input terminal is coupled to the third output terminal and the third input terminal is coupled to the second output terminal; otherwise, the second input terminal is coupled to the second output terminal and the third input terminal is coupled to the third output terminal. The third output terminal, second input line and second output line are coupled to each other. The input signal carried on the first input line is set as 0 so that the second output line and the first output line have the same output.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: September 23, 2008
    Assignee: National Tsing Hua University
    Inventors: Chun Yao Wang, Min Lun Chuang