Patents by Inventor Min Miao

Min Miao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240372964
    Abstract: Low lighting adjustments can be provided within a video communication session. A system generates a lighting adjustment request including a lighting adjustment depth, then segments a region of a video frame into texture sub-regions. The system smoots areas that are adjacent to the texture sub-regions. The system detects an amount of lighting using an artificial intelligence model and modifies the video frame to adjust the amount of lighting. The amount of adjustment of lighting corresponds to the lighting adjustment depth.
    Type: Application
    Filed: July 19, 2024
    Publication date: November 7, 2024
    Inventors: Abhishek Balaji, Bo Ling, Min Miao, Nitasha Walia, Xingguo Zhu
  • Patent number: 12081904
    Abstract: Methods and systems provide for low lighting adjustments within a video communication session. First, the system receives video content within a video communication session of a video communication platform, the video content having multiple video frames. The system then receives or generates a lighting adjustment request including a lighting adjustment depth, then detects an amount of lighting in the video content. The system then modifies the video content to adjust the amount of lighting, wherein the amount of adjustment of lighting corresponds to the adjustment depth, and wherein adjusting the amount of lighting is performed in real time or substantially real time upon receiving the lighting adjustment request.
    Type: Grant
    Filed: July 31, 2021
    Date of Patent: September 3, 2024
    Assignee: Zoom Video Communications, Inc.
    Inventors: Abhishek Balaji, Bo Ling, Min Miao, Nitasha Walia, Xingguo Zhu
  • Publication number: 20230421721
    Abstract: Methods and systems provide for low lighting adjustments within a video communication session. First, the system receives video content within a video communication session of a video communication platform, the video content having multiple video frames. The system then receives or generates a lighting adjustment request including a lighting adjustment depth, then detects an amount of lighting in the video content. The system then modifies the video content to adjust the amount of lighting, wherein the amount of adjustment of lighting corresponds to the adjustment depth, and wherein adjusting the amount of lighting is performed in real time or substantially real time upon receiving the lighting adjustment request.
    Type: Application
    Filed: July 31, 2021
    Publication date: December 28, 2023
    Inventors: Abhishek Balaji, Bo Ling, Min Miao, Nitasha Walia, Xingguo Zhu
  • Publication number: 20230031897
    Abstract: Methods and systems provide for low lighting adjustments within a video communication session. First, the system receives video content within a video communication session of a video communication platform, the video content having multiple video frames. The system then receives or generates a lighting adjustment request including a lighting adjustment depth, then detects an amount of lighting in the video content. The system then modifies the video content to adjust the amount of lighting, wherein the amount of adjustment of lighting corresponds to the adjustment depth, and wherein adjusting the amount of lighting is performed in real time or substantially real time upon receiving the lighting adjustment request.
    Type: Application
    Filed: July 31, 2021
    Publication date: February 2, 2023
    Inventors: Abhishek Balaji, Bo Ling, Min Miao, Nitasha Walia, Xingguo Zhu
  • Publication number: 20180077115
    Abstract: Examples disclosed herein relate, among other things, to a computing device. The computing device may include an alias engine to obtain an identifier of an electronic device, to determine, based on the identifier, at least one dictionary term, and generate, based on the dictionary term, an alias string. The computing device may also include an output engine to store the alias string in association with the electronic device.
    Type: Application
    Filed: May 29, 2015
    Publication date: March 15, 2018
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Jun-Min Miao, Wei Wu
  • Patent number: 9040412
    Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method therefor. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face. An adhesive material is used for adhesion between adjacent layers of the chips while each layer of the chips contains a substrate layer and a dielectric layer from bottom to top. A front surface of the chip has a first concave, which is filled with metal to form a first electrical conductive ring that connects to microelectronic devices inside the chip via a redistribution layer. A first through layers of chips hole with a first micro electrical conductive pole inside, penetrates the stacked chips. The structure in the present invention enhances the electric interconnection and the bonding between adjacent layers of chips while the instant fabricating method simplifies the process and increases the yield.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: May 26, 2015
    Assignee: PEKING UNIVERSITY
    Inventors: Shenglin Ma, Yunhui Zhu, Xin Sun, Yufeng Jin, Min Miao
  • Publication number: 20140342502
    Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Shenglin MA, Yunhui ZHU, Xin SUN, Yufeng JIN, Min MIAO
  • Patent number: 8836140
    Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: September 16, 2014
    Assignee: Peking University
    Inventors: Shenglin Ma, Min Miao, Yunhui Zhu, Xin Sun, Yufeng Jin
  • Publication number: 20130093091
    Abstract: The present invention discloses a three-dimensional vertically interconnected structure and a fabricating method for the same. The structure comprises at least two layers of chips which are stacked in sequence or stacked together face to face, and an adhesive material is used for adhesion between adjacent layers of said chips, each layer of chips contains a substrate layer and a dielectric layer sequentially bottom to top; an front surface of the chip has a first concave with an annular cross section, and the first concave is filled with metal inside to form a first electrical conductive ring connecting to microelectronic devices inside the chip via a redistribution layer; a first through layers of chips hole having the same radius and center as inner ring of the first electrical conductive ring penetrates the stacked chips and has a first micro electrical conductive pole inside that is electrically connected to the first electrical conductive ring.
    Type: Application
    Filed: August 5, 2011
    Publication date: April 18, 2013
    Applicant: PEKING UNIVERSITY
    Inventors: Shenglin Ma, Yunhui Zhu, Xin Sun, Yufeng Jin, Min Miao
  • Publication number: 20090040326
    Abstract: Methods and apparatuses for supplying current to an electronic device include incrementally changing an output current supplied to the device according to a digital sequence.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Inventors: Tien-Min Miao, Chiajen Michael Lee
  • Publication number: 20060006915
    Abstract: An imager with a slew rate control circuit that uses multiple digital control signals to control the rising and falling slew rates of boosted signals, such as transistor gate signals, and/or supply voltages used by an imager or other device. By using digital signals, the invention provides slew rate control that is less affected by power supply, temperature and process variations.
    Type: Application
    Filed: July 12, 2004
    Publication date: January 12, 2006
    Inventors: Hai Yan, Chiajen Lee, Geetanjali Asuri, Tien-Min Miao, Siri Eikedal, Christopher Zeleznik, Kwang-Bo Cho, Gennadiy Agranov