Abstract: A data storage device includes a storage and a memory controller. The storage is configured to store data. The memory controller generates meta-data including a mapping relationship between a logical address used in an external device and a physical address used in the storage. The memory controller generates a normal meta-slice having a first size including the meta-data in a first operation mode. The memory controller stores a meta-page including the normal meta-slice in the storage. The memory controller generates a modified meta-slice having a second size as a part of the normal meta-slice in the second operation mode. The memory controller stores a meta-page including the modified meta-slice and context data corresponding to size information of the modified meta-slice in the storage. The memory controller restores the meta-data based on the context data in a power-on mode.

Abstract: A data storage device includes a storage and a memory controller. The storage is configured to store data. The memory controller generates meta-data including a mapping relationship between a logical address used in an external device and a physical address used in the storage. The memory controller generates a normal meta-slice having a first size including the meta-data in a first operation mode. The memory controller stores a meta-page including the normal meta-slice in the storage. The memory controller generates a modified meta-slice having a second size as a part of the normal meta-slice in the second operation mode. The memory controller stores a meta-page including the modified meta-slice and context data corresponding to size information of the modified meta-slice in the storage. The memory controller restores the meta-data based on the context data in a power-on mode.

Abstract: The present disclosure relates to an electronic device. A memory controller controlling a memory package including a plurality of memory dies each including a plurality of memory blocks, the plurality of memory blocks controlled in units of super blocks each including at least one memory block selected from each of the plurality of memory dies includes a reclaim information storage storing reclaim information including read counts and migration level information related to the read counts, and a read reclaim controller migrating data stored in a target block having a read count exceeding a threshold count, and victim blocks selected according to the reclaim information to another super block different from a super block to which the target block belongs, wherein the victim blocks include memory blocks whose migration level information is the highest among memory blocks included in memory dies different from a memory die including the target block.

Abstract: The present disclosure relates to an electronic device. A memory controller controlling a memory package including a plurality of memory dies each including a plurality of memory blocks, the plurality of memory blocks controlled in units of super blocks each including at least one memory block selected from each of the plurality of memory dies includes a reclaim information storage storing reclaim information including read counts and migration level information related to the read counts, and a read reclaim controller migrating data stored in a target block having a read count exceeding a threshold count, and victim blocks selected according to the reclaim information for another super block different from a super block, wherein the victim blocks include memory blocks whose the migration level information is the largest among memory blocks included in memory dies different from a memory die including the target block.

Abstract: Disclosed are a memory system, a memory controller and a method for operating a memory controller. The memory controller manages statuses of respective pages by referring to a first memory and a second memory, the first memory stores a valid page table which includes valid page checking information of the respective pages, and the second memory caches a cache table which includes information for updating a part of the valid page table and has a size smaller than the valid page table, whereby it is possible to improve write performance through effective management of page status information.

Abstract: A memory system includes: a memory device storing host data provided from a host; and a memory controller managing and transferring the host data between the host and the memory device, wherein the memory controller comprises: a write buffer temporarily storing the host data to be transferred to the memory device; a buffer monitoring device checking a usage amount of the write buffer during a predetermined period; a buffer usage comparing device generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and a first flush device transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.

Abstract: Disclosed are a memory system, a memory controller and a method for operating a memory controller. The memory controller manages statuses of respective pages by referring to a first memory and a second memory, the first memory stores a valid page table which includes valid page checking information of the respective pages, and the second memory caches a cache table which includes information for updating a part of the valid page table and has a size smaller than the valid page table, whereby it is possible to improve write performance through effective management of page status information.

Abstract: A memory system includes: a memory device storing host data provided from a host; and a memory controller managing and transferring the host data between the host and the memory device, wherein the memory controller comprises: a write buffer temporarily storing the host data to be transferred to the memory device; a buffer monitoring device checking a usage amount of the write buffer during a predetermined period; a buffer usage comparing device generating a flush control signal based on a usage amount comparison result by comparing the usage amount checked during a current period corresponding to the predetermined period with the usage amount checked during a previous period corresponding to the predetermined period; and a first flush device transferring the host data temporarily stored in the write buffer to the memory device in response to the flush control signal.

Abstract: A memory system includes a memory device including a plurality of memory chips each including a plurality of memory blocks grouped as one or more super blocks, wherein the memory blocks each include a plurality of pages suitable for storing write data requested from a host, and a controller suitable for checking a size of the write data and free pages of the super blocks, determining a first super block corresponding to the checked size of the write data based on the checked free pages among the super blocks, and programming the write data in memory blocks of the first super block.

Abstract: A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.

Abstract: A memory system includes a memory device including a plurality of memory chips, each of which includes a plurality of planes suitable for storing data and a plurality of page buffers respectively corresponding to the planes; and a controller suitable for transferring write data stored in a write buffer thereof to a first page buffer of a first chip, releasing the write buffer and a first plane corresponding to the first page buffer in the first chip after the transfer to the first page buffer, and programming the write data in the first planes after the release from the first plane.

Abstract: A memory system includes a memory device including a plurality of memory chips each including a plurality of memory blocks grouped as one or more super blocks, wherein the memory blocks each include a plurality of pages suitable for storing write data requested from a host, and a controller suitable for checking a size of the write data and free pages of the super blocks, determining a first super block corresponding to the checked size of the write data based on the checked free pages among the super blocks, and programming the write data in memory blocks of the first super block.