Abstract: A high speed data communication controller comprising two independent central processing units, each having its own independent program instruction fetch data path, and instruction execution data path. The data communication controller includes a dual-port serial communication subsystem and a bus interface unit operably associated with a four channel DMA controller. One central processing unit is assigned the task of handling the medium access control (MAC) layer function of a multilayered local area network protocol, while the other central processing unit handles host commands and buffer memory management functions associated with the transmission and reception of packets relating to the higher layer protocol. As a result of the present invention, efficient data communication processing is achieved within a single VSLI chip, thereby improving node and network data throughout.