Patents by Inventor Min Pei

Min Pei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250031404
    Abstract: A semiconductor device may include one or more transistor structures that include a plurality of source/drain regions and a gate structure between the source/drain regions. The semiconductor device may further include one or more dielectric layers between a source/drain contact structure and a gate structure of the one or more of the transistor structures. The one or more dielectric layers may be manufactured using on oxidation treatment process to tune the dielectric constant of the one or more dielectric layers. The dielectric constant of the one or more dielectric layers may be tuned to reduce the parasitic capacitance between the source/drain contact structure and the gate structure (which are conductive structures). In particular, the dielectric constant of the one or more spacer dielectric may be tuned using the oxidation treatment process to lower the as-deposited dielectric constant of the one or more dielectric layers.
    Type: Application
    Filed: July 21, 2023
    Publication date: January 23, 2025
    Inventors: Min-Hsuan LU, Sheng-Tsung WANG, Huan-Chieh SU, Tzu Pei CHEN, Hao-Heng LIU, Chien-Hung LIN, Chih-Hao WANG
  • Publication number: 20240413054
    Abstract: Integrated circuit packages with fluid spacers to improve pin load distribution are disclosed. An example apparatus includes an integrated circuit (IC) package, a circuit board, a socket to couple the IC package and the circuit board, a backplate coupled to the circuit board, a loading assembly to provide a stack load to the IC package, and a fluid liner positioned between the circuit board and the backplate.
    Type: Application
    Filed: August 20, 2024
    Publication date: December 12, 2024
    Applicant: Intel Corporation
    Inventors: Min Pei, Ralph V. Miele, Lejie Liu, Phil Geng, Caleb Million Tessema
  • Publication number: 20240407092
    Abstract: Covers for integrated circuit package sockets are disclosed herein. An example cover for a socket for an integrated circuit package includes a base including a cutout, the cutout to engage a pin associated with the socket, engagement of the cutout and the pin to maintain a position of the cover relative to the socket; and a handle to facilitate positioning of the cover to move the cutout into engagement with the pin.
    Type: Application
    Filed: August 15, 2024
    Publication date: December 5, 2024
    Applicant: Intel Corporation
    Inventors: Ariatne Ramirez Macias, Allison Van Horn, Kristin L. Weldon, Israel Cruz Ruiz, Fernando Gonzalez Lenero, Min Pei, Francisco Javier Colorado Alonso, Randall Scott Sanford, Emery Evon Frey, Eric W. Buddrius
  • Publication number: 20240133945
    Abstract: A low level contact resistance (LLCR) testing apparatus comprises a test board, an interface board, and a patch board. The test board comprises a processor socket. The interface board connects to both the test board and the patch board. The patch board connects to a contact resistance tester. An LLCR system comprising the LLCR testing apparatus and a contact resistance tester can be portable. The test board can accommodate thermal management solutions of varying sizes and types. Different test board designs can accommodate different socket-processor configurations and the different test boards can be easily accommodated by an LLCR testing apparatus due to its modular design.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Mohanraj Prabhugoud, David Shia, Lejie Liu, Silver Alfonso Rodriguez Estrada, Min Pei, Ralph V. Miele, Caleb Million Tessema
  • Publication number: 20230209702
    Abstract: Warpage reduction through laminate glass cloth design modification is described herein. In one example, a substrate for a microelectronic assembly, includes one or more glass-cloth containing layers. At least one of the glass-cloth containing layers includes a glass cloth having a weave including: a first plurality of parallel glass fibers, a second plurality of parallel glass fibers, and a third plurality of parallel glass fibers interwoven with one another in a plane. The second plurality of parallel glass fibers crosses the first plurality of glass fibers at a first angle, and the third plurality of parallel glass fibers crosses the first plurality of glass fibers at a second angle and crosses the second plurality of glass fibers at a third angle. In one example, the glass cloth weave includes a hexagonal pattern.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Satyajit WALWADKAR, Min PEI, George HSIEH
  • Publication number: 20230014898
    Abstract: Methods, apparatus, systems, and articles of manufacture to improve pin contact are disclosed. An apparatus disclosed herein includes a back plate, a circuit board disposed between the back plate and a socket, and a spring sheet disposed between the back plate and the circuit board.
    Type: Application
    Filed: September 28, 2022
    Publication date: January 19, 2023
    Inventors: Phil Geng, Jordan Johnson, Mengqi Liu, Ralph Miele, Min Pei
  • Publication number: 20170287757
    Abstract: Devices and methods are shown that use sensors to detect physical characteristics of an IC circuit or other device over time. The physical characteristics and time data may be used to calculate a damage metric of the IC circuit or other device. The damage metric may be used to notify a user about a condition of the IC circuit or other device.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Inventors: Robert F. Kwasnick, Min Pei, Alan E. Lucero
  • Publication number: 20140168909
    Abstract: Attachment structures for electrically coupling a microelectronic package to a microelectronic board/interposer including joint pads formed on the microelectronic board/interposer which provide a gap between respective openings in a solder resist layer of the microelectronic substrate and each of the joint pads. Such attachment structures may reduce or substantially eliminate contact between a solder interconnect and a solder resist layer of the microelectronic board/interposer, which may, in turn, reduce or substantially eliminate the potential of crack initiation and propagation at contact areas between the solder interconnect and a solder resist layer of the microelectronic board/interposer due to stresses induced by a mismatch of thermal expansion between the microelectronic package and the microelectronic board/interposer during thermal cycling.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Inventors: Tieyu Zheng, Jin A. Zhao, Ru Han, Min Pei