Patents by Inventor Min-Sea Liu

Min-Sea Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5629235
    Abstract: The present invention is related to a method for forming a damage-free buried contact. The method according to the present invention includes steps of a) providing a silicon substrate; b) forming an oxide layer on the silicon substrate; c) forming a first conductive layer on the oxide layer; d) defining a buried contact region on the first conductive layer on the first conductive layer; e) removing a portion of the first conductive layer according to a shape of the buried contact region; f) implanting ions in the buried contact region to form an ion-implantation region under the oxide layer; and f) removing a portion of the oxide layer to obtain the buried contact. The step f) can be executed either before or after the step f). The present invention provides a method for forming a buried contact by which trench will not be occurred on the silicon substrate during the etching process thereof, so that a damage-free buried contact can be obtained.
    Type: Grant
    Filed: July 5, 1995
    Date of Patent: May 13, 1997
    Assignee: Winbond Electronics Corporation
    Inventor: Min-Sea Liu
  • Patent number: 5622884
    Abstract: A method is provided for manufacturing a polysilicon load resistor of a semiconductor memory cell. The semiconductor memory cell is formed with at least one transistor and has a semiconductor substrate with a gate dielectric layer on a portion thereof, and a gate electrode layer over the gate dielectric layer.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: April 22, 1997
    Assignee: Winbond Electronics Corp.
    Inventor: Min-Sea Liu
  • Patent number: 5550085
    Abstract: A method of forming damage-free buried contacts in a semiconductor substrate without the trenches and pitted areas can be carried out by forming a silicon oxide layer as a gate dielectric layer on top of the substrate, forming a first polysilicon layer on top of the silicon oxide layer, anisotropically etching away the first polysilicon layer by using a first mask and a first etching gas that has high etching selectivity between polysilicon and silicon oxide such that a first portion of the polysilicon layer is left on the top surface of the substrate except the area defining a buried contact, forming in the substrate a zone of a second conductivity type at the area defining the buried contact by implanting impurity ions, removing the silicon oxide layer over the area defining the buried contact and removing the masking layer over the first portion of the polysilicon layer, depositing sequentially a conducting layer and a second polysilicon layer, anisotropically etching the second polysilicon layer over an a
    Type: Grant
    Filed: September 7, 1995
    Date of Patent: August 27, 1996
    Assignee: Winbond Electronics Corp.
    Inventor: Min-Sea Liu