Abstract: A semiconductor package includes a first redistribution structure including a first redistribution layer, a first semiconductor chip on the first redistribution structure, an insulating layer adjacent a sidewall of the first semiconductor chip on the first redistribution structure and spaced apart from the first semiconductor chip in a horizontal direction, a connection structure extending through the insulating layer in a vertical direction and electrically connected to the first redistribution layer, a first molding layer on a sidewall and a top surface of the first semiconductor chip, and a second molding layer directly on each of a top surface of the insulating layer and a top surface of the first molding layer. The second molding layer includes a material different from a material of the first molding layer, and the top surface of the first semiconductor chip is lower than the top surface of the insulating layer.

Abstract: A semiconductor package includes a frame including wiring layers and having a recess portion in which a stopper layer is disposed on a bottom surface, a semiconductor chip having an active surface and an inactive surface, the inactive surface being disposed in the recess portion and facing the stopper layer, a first connection portion on the connection pad, a second connection portion on the uppermost wiring layer, a stiffener on the upper surface of the frame and surround at least a portion of the second connection portion, the stiffener being spaced apart from second connection portion, an encapsulant covering at least portions of each of the frame and the semiconductor chip, and filling at least a portion of the recess portion, and a connection structure on the frame and the semiconductor chip, and including a redistribution layer electrically connected to the first and second connection portions.

Abstract: A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes. A semiconductor chip and passive components are disposed in the one or more through-holes of the frame on the connection structure. A first encapsulant covers at least portions of the passive components and the frame. A frame wiring layer is disposed on the frame, and a location identifying mark is disposed around the semiconductor chip on the frame and is spaced apart from the frame wiring layer. At least a portion of the location identifying mark is not covered by the first encapsulant.

Abstract: A fan-out semiconductor package includes: a first semiconductor chip having an active surface having first connection pads disposed thereon and an inactive surface opposing the active surface; a second semiconductor chip having an active surface having second connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of each of the first and second semiconductor chips; and a connection member disposed on the active surface of each of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second connection pads, wherein the first and second semiconductor chips are physically integrated with each other, and the first and second semiconductor chips have internal circuits, respectively.

Abstract: A semiconductor package includes a connection structure including an insulating layer, a wiring layer disposed on the insulating layer, and a connection via penetrating through the insulating layer and connected to the wiring layer. A frame is disposed on the connection structure and has one or more through-holes. A semiconductor chip and passive components are disposed in the one or more through-holes of the frame on the connection structure. A first encapsulant covers at least portions of the passive components and the frame. A frame wiring layer is disposed on the frame, and a location identifying mark is disposed around the semiconductor chip on the frame and is spaced apart from the frame wiring layer. At least a portion of the location identifying mark is not covered by the first encapsulant.

Abstract: A semiconductor package includes a frame including wiring layers and having a recess portion in which a stopper layer is disposed on a bottom surface, a semiconductor chip having an active surface and an inactive surface, the inactive surface being disposed in the recess portion and facing the stopper layer, a first connection portion on the connection pad, a second connection portion on the uppermost wiring layer, a stiffener on the upper surface of the frame and surround at least a portion of the second connection portion, the stiffener being spaced apart from second connection portion, an encapsulant covering at least portions of each of the frame and the semiconductor chip, and filling at least a portion of the recess portion, and a connection structure on the frame and the semiconductor chip, and including a redistribution layer electrically connected to the first and second connection portions.

Abstract: A fan-out semiconductor package includes: a first semiconductor chip having an active surface having first connection pads disposed thereon and an inactive surface opposing the active surface; a second semiconductor chip having an active surface having second connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of each of the first and second semiconductor chips; and a connection member disposed on the active surface of each of the first and second semiconductor chips and including a redistribution layer electrically connected to the first and second connection pads, wherein the first and second semiconductor chips are physically integrated with each other, and the first and second semiconductor chips have internal circuits, respectively.