Abstract: A free motion headform (FMH) impact performance prediction device using artificial intelligence includes a data processing processor configured to generate an image by extracting a pre-processed test target image, generated by pre-processing test target design data, using a pre-trained model and generate a pre-processed test target distance value by pre-processing the test target design data. The FMH input performance prediction device also includes a machine learning processor configured to concatenate the image generated by extraction on the basis of the pre-trained model and the pre-processed test target distance value and to predict impact performance using a neural network in which parameters are updated by learning based on an image obtained by pre-processing existing design data and existing impact amount data corresponding to the existing design data. The FMH input performance prediction device further includes an output processor configured to output a value learned by the machine learning processor.

Abstract: Provided is a time-to-digital converter, comprising a phase frequency detector configured to receive a phase-locked loop input clock and a feedback clock, a ring oscillator configured to perform oscillation with multi-phase clocks of a first period, a counter array configured to count the number of oscillations in which the ring oscillator oscillates in a first period by the number of positive integers during the first pulse width, a multiplexer configured to divide the first period into a plurality of zones using edge information of the multi-phase clocks of the ring oscillator, and selects and outputs voltage information of a plurality of neighboring phase clocks included in a first zone from the plurality of zones, an analog-to-digital converter, a calibrator, and a first adder, wherein the calibrator comprises, an offset lookup table generation circuit, a gain-corrected analog-to-digital conversion output generator, and a second adder.

Abstract: The present invention relates to a time-division duplex (TDD) antenna apparatus which can reduce signal loss, and thereby minimize the noise figure (NF) of a system and extend uplink coverage of the system, by separating a transmitter circuit from a receiver circuit of the antenna apparatus, and disposing a low noise amplifier (LNA) of the receiver circuit between a reception antenna and a reception filter of the receiver. A time-division duplex antenna apparatus according to an embodiment of the present invention includes: a transmitter which includes at least one transmission antenna module and transmits a downlink signal through a first path; a receiver which includes at least one reception antenna module and receives an uplink signal through a second path that is separated from the first path without any overlapping portions thereof; and a controller which controls the transmitter and the receiver in a time-division duplex manner.

Abstract: A fabricating method for a test element group is provided. The fabricating method for a test element group includes fabricating test areas generated in a scribe lane area, wherein fabricating of the test areas includes forming a plurality of fins protruding in a first direction on a substrate, covering at least some of the plurality of fins with a masking material, and performing selective epitaxial growth by injecting a gas onto the plurality of fins. The gas is not injected onto the at least some of the plurality of fins that are covered with the masking material, such that the epitaxial growth does not occur on the fins covered with the masking material.

Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.

Abstract: A method of detecting failure of a semiconductor device includes forming an active fin on an active region of a substrate, the active fin extending in a first direction, forming a gate structure on the active fin, the gate structure extending in a second direction intersecting the first direction, forming source/drain layers on respective portions of the active fins at opposite sides of the gate structure, forming a wiring to be electrically connected to the source/drain layers, and applying a voltage to measure a leakage current between the source/drain layers. Only one or two active fins may be formed on the active region. Only one or two gate structures may be formed on the active fin.