Patents by Inventor Min-Seog Han

Min-Seog Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6215143
    Abstract: A DRAM cell capacitor is provided, having HSG (hemispherical grain) silicon disposed on a selected portion of a storage node. The capacitor resembles a solid cylindrical configuration having a top portion, a side wall, and a top edge portion sloped downward from the top portion to the side wall. HSG silicon is disposed only on the top portion and the side wall, but not on the sloped top edge portion.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: April 10, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Seog Han, Ji-Chul Shin, Seok Woo Nam, Hyung-Seok Lee
  • Patent number: 6013549
    Abstract: A DRAM cell capacitor is provided wherein a capacitor bottom electrode has an HSG (Hemi-Spherical Grain) layer formed thereon so as to increase capacitance of the capacitor. In the DRAM cell capacitor, the capacitor bottom electrode has an angled shape at a top edge thereof, and the HSG silicon layer is not formed on the top edge of the capacitor bottom electrode. A method for manufacturing the DRAM cell capacitor comprises etching an upper portion of the conductive layer using the photoresist pattern as a mask, and at the same time forming a polymer on both sidewalls of the photoresist pattern to etch the upper portion thereof and thereby to make a top edge of the conductive layer be angled. The method further comprises etching a remaining portion of the conductive layer sing a combination of the photoresist pattern and the polymer as a mask until an upper surface of the interlayer insulating layer is exposed, to thereby form the capacitor bottom electrode.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: January 11, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Seog Han, Ji-Chul Shin, Seok Woo Nam, Hyung-Seok Lee
  • Patent number: 5476807
    Abstract: A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: December 19, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kang-hyun Lee, Jong-seo Hong, Hyoung-sub Kim, Jae-ho Kim, Min-seog Han