Abstract: An image sensor includes: a pixel of a first tab; a pixel of a second tab; an operation amplifier suitable for comparing, in a comparison operation, a pixel signal of the first tab and a pixel signal of the second tab with each other to produce a comparison result, receiving, in an auto-zeroing operation, a ramp voltage and a selected pixel signal which is selected based on the comparison result between the pixel signal of the first tab and the pixel signal of the second tab, and receiving, in an analog-to-digital conversion operation, the ramp voltage and an unselected pixel signal which is not selected from the pixel signal of the first tab and the second pixel signal of the second tab; and a counter circuit suitable for generating a digital code based on an output of the operation amplifier.

Abstract: An image sensing device includes a pixel array including a unit pixel suitable to transfer and store charges in response to a transfer signal and read out a pixel signal corresponding to the stored charges in response to a selection signal provided to the unit pixel; a signal converter suitable for comparing the pixel signal with a ramp signal based on a switch signal to generate a distance information signal; and a signal controller suitable for generating the switch signal for initializing the signal converter in a temporal section where the pixel signal is read out.

Abstract: An image sensing device includes an optical emitter outputting a modulated signal to a target object; an optical receiver generating, according to a phase control signal, pixel signals corresponding to a reflected signal from the target object; an image processor calculating a depth phase based on the pixel signals and compensating for the depth phase according to a phase offset signal to output a depth information signal; a driving control circuit generating the phase control signal corresponding to a phase of the modulated signal and setting an initial phase difference between the modulated signal and the phase control signal according to the phase offset signal; and an offset calculating circuit setting a plurality of reference phases, selecting a reference phase closest to the depth phase among the set reference phases and generating the phase offset signal representing a phase difference between the selected reference phase and the depth phase.

Abstract: Disclosed is an image sensing device including a first clock distributor suitable for receiving a first input dock signal through a first input terminal, and outputting a plurality of first output clock signals through a plurality of first output terminals, and a first conductive line coupled in common to the plurality of first output terminals.

Abstract: An image sensor including a pixel of a first tap. a pixel of a second tap. an operational amplifier configured to perform an auto zeroing operation with a pixel signal of the pixel of the second tap applied, and perform an operation for comparison between a ramp voltage and a signal output from the pixel of the first tap, with a pixel signal of the pixel of the first tap applied, and a counter circuit configured to generate a digital code in response to an output of the operational amplifier.

Abstract: An analog-to-digital converter circuit includes: a first operation amplifier suitable for comparing a ramp voltage and a voltage to be converted so as to produce an amplification result and outputting the amplification result; a second operation amplifier suitable for comparing the amplification result transferred to a first input terminal with a reference voltage transferred to a second input terminal so as to produce a comparison result and outputting the comparison result; a leakage current measurer suitable for measuring a leakage current to the first input terminal; and a leakage current generator suitable for causing a current of the same amount as that of the leakage current measured by the leakage current measurer to flow to the second input terminal.

Abstract: An image sensor includes: first lines transferring a first clock having the same phase as that of modulated light in a first phase and a third clock having a phase difference of a ½ cycle from the phase of the modulated light in a second phase; second lines transferring the third clock in the first phase and the first clock in the second phase; third lines transferring a second clock having a phase difference of a ¼ cycle from the phase of the modulated light in the first phase and a fourth clock having a phase difference of a ¾ cycle from the phase of the modulated light in the second phase; fourth lines transferring the fourth clock in the first phase and the second clock in the second phase; and a pixel array including first pixels and second pixels that are alternately arranged in row and column directions.

Abstract: An image sensor includes a pixel array including plural first pixels and a second pixel, and a row decoder configured to supply a second row selection signal to the second pixel and a first pixel that is coupled to the same column line as the second pixel and is accessed simultaneously with the second pixel in a binning mode, and supply a first row selection signal to a remaining first pixel.

Abstract: Disclosed is an image sensing device including a plurality of current cells whose total number to be used is adjusted based on a plurality of enable signals, and which are sequentially controlled based on a reset signal and a plurality of selection signals; a current-voltage conversion circuit suitable for converting a plurality of unit currents, which are supplied from current cells used among the plurality of current cells, into a ramp signal; and a first control circuit suitable for generating the plurality of enable signals based on a maximum conversion code value corresponding to a slope of the ramp signal.

Abstract: Disclosed is an image sensing device and an operating method thereof, and the image sensing device may include a light detection circuit coupled between a low voltage terminal and a first node, a first transmission circuit coupled between the first node and a second node, a storage circuit coupled between the second node and a third node, a first coupling circuit coupled between the third node and a high voltage terminal, a second transmission circuit coupled between the third node and the first node, and a second coupling circuit coupled between the second node and the high voltage terminal.

Abstract: An image sensing device includes at least one unit pixel including a plurality of pixels for generating a plurality of pixel signals based on a plurality of control signals having different phases, and an equalizing circuit suitable for equalizing noise that occurs in the plurality of pixels during a reset operation on the unit pixel.

Abstract: An image sensing device includes a pixel suitable for outputting a pixel signal through a read-out line during a read-out section and a precharge block suitable for precharging the read-out line to a voltage level corresponding to an initial voltage level of the pixel signal during a row non-selection section adjacent to the read-out section.

Abstract: Disclosed are devices, systems and methods for allowing a ramp signal generator to reduce noise. A ramp signal generator may include a reference voltage generator configured to generate a reference voltage, a gain controller configured to control a gain of the reference voltage, a ramp signal controller configured to generate a ramp signal in response to an output signal of the gain controller, and an offset controller coupled to an output terminal of the gain controller in the form of a current mirror, and control an offset of the ramp signal in response to a control signal.

Abstract: A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.

Abstract: An image sensor includes a pixel array including plural first pixels and a second pixel, and a row decoder configured to supply a second row selection signal to the second pixel and a first pixel that is coupled to the same column line as the second pixel and is accessed simultaneously with the second pixel in a binning mode, and supply a first row selection signal to a remaining first pixel.

Abstract: Disclosed are devices, systems and methods for allowing a ramp signal generator to reduce noise. A ramp signal generator may include a reference voltage generator configured to generate a reference voltage, a gain controller configured to control a gain of the reference voltage, a ramp signal controller configured to generate a ramp signal in response to an output signal of the gain controller, and an offset controller coupled to an output terminal of the gain controller in the form of a current mirror, and control an offset of the ramp signal in response to a control signal.

Abstract: A data readout apparatus may include a comparison circuit structured to compare a pixel signal with the ramp signal to generate a comparison result, a counter array structured to receive the comparison results to count up with each clock pulse from a first timing until a second timing to convert a counted number of clock pulses into differential data and output the differential data through differential data lines, and a sense amplifier array structured to receive the differential data to sense and amplify the differential data based on a judge clock. The sense amplifier array can include a replica delay structured to delay the judge clock and the precharge pulse signal based on a read out timing and read out the data from the counter array at the read out timing.

Abstract: A data readout apparatus may include a comparison circuit structured to compare a pixel signal with the ramp signal to generate a comparison result, a counter array structured to receive the comparison results to count up with each clock pulse from a first timing until a second timing to convert a counted number of clock pulses into differential data and output the differential data through differential data lines, and a sense amplifier array structured to receive the differential data to sense and amplify the differential data based on a judge clock. The sense amplifier array can include a replica delay structured to delay the judge clock and the precharge pulse signal based on a read out timing and read out the data from the counter array at the read out timing.

Abstract: A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.

Abstract: A differential circuit includes a differential selection block suitable for generating differential selection signals corresponding to differential input signals in response to an enable signal and a differential loading block suitable for loading differential output signals corresponding to the differential input signals on differential lines in response to the differential selection signals.