Abstract: A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture.

Abstract: A scribe line structure of a semiconductor wafer is provided in the invention. The semiconductor wafer has a plurality of substantially parallel horizontal scribe lines and a plurality of substantially parallel vertical scribe lines to separate a plurality of chips from each other. According to the invention, each parallel horizontal scribe line and each parallel vertical scribe line are divided along two elongated sides thereof into a plurality of portions with the same rectangular area. Each of the plurality of portions of each scribe line is composed of the scribe line structure. The scribe line structure comprises a multi-layer structure with four sides formed over whole area of each portion of each scribe line and at least two rows of cavities formed along the four sides of the multi-layer structure. The cavities of the scribe line structure are capable of relieving internal stress of the scribe lines and arresting possible cracks induced during scribe line manufacture.

Abstract: An inter-metal dielectric (IMD) layer structure and its forming method are disclosed. The IMD layer structure is formed between a first conducting layer and a second conducting layer and includes a first dielectric layer overlying the first conducting layer, a glass layer overlying the first dielectric layer, an etching stop layer overlying the glass layer, and a second dielectric layer overlying the etching stop layer under the second conducting layer. The etching rate of the etching stop layer is relatively low so that it can prevent the glass layer etched out. Therefore, a long-time etching can be used to obtain a better through hole profile.

Abstract: A process for forming shallow trench isolation (STI) structures. It includes the steps of: (a) depositing a composite silicon nitride on to the silicon substrate; (b) forming a shallow trench on the silicon substrate by etching, using the composite silicon nitride as the hard mask; (c) depositing a filler oxide layer inside the shallow trench as well as on top of the composite silicon nitride, using a chemical vapor deposition (CVD) method; and (d) using a chemical-mechanical polishing (CMP) process to planarize the filler oxide layer using the composite nitride as a CMP stop. The composite silicon nitride comprises a plurality of silicon nitride layers whose CMP removal rate increases with the distance from the silicon substrate. Additionally, a composite silicon oxide layer can be formed on top of the filler oxide layer which comprises a plurality of silicon oxide layers whose CMP removal rate increases with the distance from the silicon substrate.

Abstract: An improved metal bonding pad is disclosed which can prevent the formation of cracks during the high temperature PECVD deposition, and the subsequent annealing, of a passivation layer which is formed to encroach the metal bonding pad and provide an encapsulation force on the metal bonding pad. The metal bonding pad comprises a plurality of stress bumpers on the periphery thereof. The stress bumpers can be hollow elongated round-cornered rectangles, pin-shaped circles, Y-shaped polygons, or ellipses. The stress bumpers, which create a discontinuous structure in the metal pad, can effectively stop stress propagation as well as relieve and re-direct stress propagation, so as to maintain the integrity of the passivation encroachment and prevent the peeling off problems often observed with the metal bonding pad.

Abstract: A method for chemically-and-mechanically polishing a semiconductor wafer surface is disclosed. It includes the steps of: (a) providing a mechanical polishing pad; (b) placing a pressure-sensitive film on top of a wafer surface to be polished by the mechanical polishing pad, the pressure-sensitive film contains materials that will show pressure-dependent colors when subject to an external pressure; (c) commencing a chemically-and-mechanically polishing process so that the mechanical polishing pad exerts a pressure on the pressure-sensitive film; (d) scanning the pressure-dependent color pattern on the pressure-sensitive film; (e) converting the pressure-dependent color pattern into a pressure distribution; and (f) adjusting the mechanical polishing pad, or a leveling of the wafer mounting, or both, according to the pressure distribution obtained in step (e).