Patents by Inventor Min-Shu Wang

Min-Shu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptive thermal ceiling control system
    Patent number: 11989005
    Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 21, 2024
    Assignee: MediaTek Inc.
    Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
  • ADAPTIVE THERMAL CEILING CONTROL SYSTEM
    Publication number: 20220334558
    Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.
    Type: Application
    Filed: September 30, 2021
    Publication date: October 20, 2022
    Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
  • TRANSPARENT TOUCH PANEL WITH IMPROVED CURED ADHESIVENESS
    Publication number: 20120021159
    Abstract: A transparent touch panel includes a light-pervious substrate, conductive traces on the light-pervious substrate, a protective layer on the conductive traces, and a cured adhesive between the conductive traces and the protective layer for bonding them together. The conductive trace has a light-pervious area to allow the ultraviolet light for curing the adhesive to pass and reach the adhesive behind the conductive trace during the ultraviolet light treatment to the adhesive, and thus improve the cured level of the adhesive.
    Type: Application
    Filed: July 18, 2011
    Publication date: January 26, 2012
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: I-HAU YEH, MIN-SHU WANG, SHIH-FENG HUANG
  • TOUCH PANEL WITH FUNCTION OF PREVENTING FAULT DETECTION
    Publication number: 20090160820
    Abstract: The present invention discloses a touch panel with function of preventing fault detection comprising a touch sensor and the outer peripheral area of the touch sensor is configured with at least one electrical lead. The present invention is characterized in having the conductive shield layer configured in a position corresponding to the outer peripheral area for preventing the fault detection by touching the outer peripheral area.
    Type: Application
    Filed: February 18, 2008
    Publication date: June 25, 2009
    Inventors: JIA-YIH LII, Yen-Chang Chiu, Min-Shu Wang, Han-Shu Lin
  • Method of test pattern generation in IC design simulation system
    Patent number: 7526703
    Abstract: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: April 28, 2009
    Assignee: Via Technologies, Inc.
    Inventors: Min-Shu Wang, Chun-You Wang, Chun-Chih Yang
  • METHOD OF TEST PATTERN GENERATION IN IC DESIGN SIMULATION SYSTEM
    Publication number: 20070101226
    Abstract: The invention provides a method of test pattern generation for an integrated circuit (IC) design simulation system, comprising merging at least 2 test vectors into a merged vector, wherein each test defines a set of test behaviors, and compiling and linking the merged vector using the IC design simulation system to generate a merged test pattern able to perform each set of test behaviors independently.
    Type: Application
    Filed: July 11, 2006
    Publication date: May 3, 2007
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Min-Shu Wang, Chun-You Wang, Chun-Chih Yang