Abstract: A semiconductor memory device includes a core block including a plurality of unit memory blocks, a peripheral circuit block including a data input/output pad, a through electrode configured to exchange signals with another semiconductor memory device, and a data input/output circuit coupled to the through electrode, the core block, and the peripheral circuit block and configured to share one receiver in order to transmit a signal from the through electrode to the peripheral circuit block and in order to transmit a signal from the through electrode to the core block.

Abstract: A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.

Abstract: A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.

Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Abstract: A semiconductor device includes a first termination circuit comprising an impedance value and configured to control the impedance value of the first termination circuit based on a first selection termination control signal and a termination control signal and a second termination circuit comprising an impedance value and configured to control the impedance value of the second termination circuit based on a second selection termination control signal and the termination control signal.

Abstract: A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Abstract: A semiconductor apparatus may include a plurality of data line sets and a multi-purpose register (MPR) configured to store at least one data set and to output the stored at least one data set as register read data through a first part of the plurality of data line sets. The semiconductor apparatus may also include a data input/output circuit configured to drive the register read data to a driver array to copy the register read data into a second part of the plurality of data line sets, wherein data line sets in the first part of the plurality of data line sets are different from data line sets in the second part of the plurality of data line sets, and wherein the driver array drives the plurality of data line sets during a write operation.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. The semiconductor device may include a second oscillation signal generation circuit for generating a second oscillation signal. The second oscillation signal generation circuit may be provided with a test voltage. The test voltage may be generated based on a burn-in test signal.

Abstract: A semiconductor device may include an input/output block suitable for operating by using a first voltage in an input mode and a second voltage in an output mode, a common input/output line coupled to the input/output block, and a voltage level maintaining block suitable for driving the common input/output line to maintain a voltage level of a transmission signal by using the first voltage in the input mode and the second voltage in the output mode.

Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.

Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.

Abstract: A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. The semiconductor device may include a second oscillation signal generation circuit for generating a second oscillation signal. The second oscillation signal generation circuit may be provided with a test voltage. The test voltage may be generated based on a burn-in test signal.

Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.

Abstract: A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.

Abstract: A semiconductor device includes a division period signal generation circuit and a clock sampling circuit. The division period signal generation circuit generates a division period signal which is enabled in synchronization with a write period that is set according to a write command and latency information. The clock sampling circuit samples an internal strobe signal to output a sampling clock signal in response to the division period signal and the internal strobe signal during a sampling period. The sampling period is set to be longer than the write period.

Abstract: A semiconductor device may include an input/output block suitable for operating by using a first voltage in an input mode and a second voltage in an output mode, a common input/output line coupled to the input/output block, and a voltage level maintaining block suitable for driving the common input/output line to maintain a voltage level of a transmission signal by using the first voltage in the input mode and the second voltage in the output mode.

Abstract: Phase control circuits are provided. The phase control circuit may include a phase controller. The phase controller may compensate for a phase difference between a first phase signal of a rising clock signal and a second phase signal of a falling clock signal to generate a first internal clock signal. The phase controller may compensate for a phase difference between a first phase signal of the falling clock signal and a second phase signal of the rising clock signal to generate a second internal clock signal. Related data output devices are also provided.

Abstract: A semiconductor device includes: a counting detection block suitable for generating a counting value of a clock signal transmitted through a first transmission path and a counting value of a target signal transmitted through a second transmission path during a counter enable section, and blocking the first transmission path and the second transmission path based on a comparison result obtained by comparing a predetermined code value with the counting value of the clock signal; and an output block suitable for outputting the counting value of the target signal corresponding to when the first and second transmission paths to a predetermined pad are blocked, based on a test mode signal.

Abstract: A semiconductor device includes: a counting detection block suitable for generating a counting value of a clock signal transmitted through a first transmission path and a counting value of a target signal transmitted through a second transmission path during a counter enable section, and blocking the first transmission path and the second transmission path based on a comparison result obtained by comparing a predetermined code value with the counting value of the clock signal; and an output block suitable for outputting the counting value of the target signal corresponding to when the first and second transmission paths to a predetermined pad are blocked, based on a test mode signal.

Abstract: A semiconductor device includes a fuse array with a plurality of fuses, a common signal generation unit suitable for receiving a power-up signal and generating an inverted power-up signal and a reset signal, a plurality of fuse registers suitable for latching a plurality of fuse data for the plurality of fuses and commonly receiving the inverted power-up signal and the reset signal from the common signal generation unit by grouped fuse registers, and an output selection unit suitable for outputting the plurality of fuse data stored on the plurality of fuse registers according to a predetermined sequence.