Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area.

Abstract: Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

Abstract: In a method for manufacturing a flash memory device, a first gate insulating film, a first gate conductive film, and a second insulating film are sequentially formed on a semiconductor substrate. A region where a first gate is to be formed is defined by etching the second insulating film to expose an upper portion of the first gate conductive film. Second conductive film spacers are formed along sidewalls of the etched second insulating film. An oxide film is formed on the exposed surface of the second conductive film spacers and the first gate conductive film. Silicon insulating spacers are formed on the sidewalls of the etched second insulating film. A source junction contact hole is formed by etching the first gate conductive film and the first gate insulating film by using the second insulating film and the silicon insulating film spacers as a mask. A source junction contact fill is formed filling the source junction contact hole.

Abstract: The present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of a later-completed flash memory to form a tip on which tunneling is centralized in an erase operation. That is, the spacer is formed on a sidewall of the silicon nitride layer pattern over the floating gate layer to form the tunneling tip.

Abstract: A split-gate flash memory includes a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and a side wall; a first junction region formed on a predetermined portion of the semiconductor substrate between two adjacent floating gates and having an opposite conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, and having a vertical side wall and a uniform width; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulato

Abstract: EEPROM devices include a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on an integrated circuit substrate, and a sense transistor gate on the tunnel insulating layer and on the gate insulating layer. The sense transistor gate includes a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate. A select transistor gate also is included on the gate insulating layer and spaced apart from the sense transistor gate.

Abstract: A split-gate flash memory includes a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and a side wall; a first junction region formed on a predetermined portion of the semiconductor substrate between two adjacent floating gates and having an opposite conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, and having a vertical side wall and a uniform width; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulato

Abstract: Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area.

Abstract: EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer.

Abstract: A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

Abstract: EEPROM devices include a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on an integrated circuit substrate, and a sense transistor gate on the tunnel insulating layer and on the gate insulating layer. The sense transistor gate includes a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate. A select transistor gate also is included on the gate insulating layer and spaced apart from the sense transistor gate.

Abstract: A split-gate flash memory includes a first gate insulating layer formed on a semiconductor substrate; a floating gate formed on the first gate insulating layer; a first spacer surrounding the floating gate and a side wall; a first junction region formed on a predetermined portion of the semiconductor substrate between two adjacent floating gates and having an opposite conductivity to that of the semiconductor substrate; a first conductive line formed on the first junction region between two adjacent first spacers; a second gate insulating layer formed on both a predetermined portion of the semiconductor substrate and the side wall of the first spacer; a word line formed on the second gate insulating layer, and having a vertical side wall and a uniform width; a second spacer formed on the vertical side wall of the word line; a second junction region formed on a portion of the semiconductor substrate adjacent the second spacer and having the same conductivity as the first junction region; an interlayer insulato

Abstract: In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

Abstract: A liquid electrophotographic printer includes a printer body. An engine unit is installed in the printer body and includes a photoreceptor belt, a laser scanner for forming a latent electrostatic image on the photoreceptor belt, a development device for developing the latent electrostatic image by supplying a developer liquid which is a mixture of a liquid carrier and a toner, a transfer roller for transferring the developed image to a print paper, a fixation roller for pressing the print paper against the transfer roller, and a drying unit for evaporating the liquid carrier remaining on the photoreceptor belt. A closed cell encompasses the engine unit. An exhaust fan exhausts the air inside the closed cell. A filter removes the gaseous carrier from the exhausted air.

Abstract: A television receiver includes a caption data display control circuit for controlling display of caption data contained an image of input standard video signal on a display screen for a wide aspect ratio in a full screen display mode for displaying the image on the entire display screen. In the caption data display control circuit, a luminance signal contained in the input standard video signal is converted into a first set of pixel values corresponding to all of the pixels consisting of the image. The second set of pixel values representing the caption data from values of pixels is then automatically detected by a detection circuit thereof from a first predetermined image region within the image. The detected second set of pixel values is converted into a caption signal denoting the caption data which is combined with the luminance signal in order to be displayed on a visible area of the display screen.