Abstract: A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.

Abstract: Proposed is a biosensor including a first specimen inlet configured to provide a space through which a specimen flows inside, an electrode element configured to measure an electromechanical signal of the flowing-in specimen, a chamber configured to provide a space in which an electrochemical reaction of the flowing-in specimen occurs, and a first specimen outlet configured to provide a space through which the flowing-in specimen flows outside, in which a moisture absorber is disposed in the chamber.

Abstract: A memory includes: a plurality of row lines; a plurality of column lines; and a plurality of memory cells each of which is coupled to one row line among the row lines and one column line among the column lines, wherein memory cells corresponding to a row line which is selected based on a row address among the row lines are simultaneously activated, and data are read from memory cells corresponding to column lines which are selected based on a column address among the activated memory cells, and the selected column lines are not adjacent to each other.

Abstract: A cryogenic semiconductor device includes isolation regions defining an active region having a first P-type ion concentration in a substrate, a gate structure in the substrate, and an ion implantation region having a second P-type ion concentration in the active region below the gate structure, wherein the gate structure includes a gate dielectric layer conformally disposed on inner sidewalls of a gate trench, a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.

Abstract: A cryogenic semiconductor device includes isolation regions defining an active region having a first P-type ion concentration in a substrate, a gate structure in the substrate, and an ion implantation region having a second P-type ion concentration in the active region below the gate structure, wherein the gate structure includes a gate dielectric layer conformally disposed on inner sidewalls of a gate trench, a lower gate electrode disposed on the gate dielectric layer, and an upper gate electrode disposed on the lower gate electrode, wherein the lower gate electrode has a relatively lower work function than the upper gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.

Abstract: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.

Abstract: A conductive silicone resin composition, and an electromagnetic wave-shielding gasket manufactured therefrom include conductive silicon carbide particles coated with a metal in a thermosetting silicone resin composition, thereby having very superior corrosion resistance, deformation resistance and thermal conductivity while maintaining electromagnetic wave-shielding efficiency.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: A junctionless semiconductor device having a buried gate, a module and system each having the same, and a method for forming the semiconductor device are disclosed. A source, a drain, and a body of a semiconductor device having a buried gate are doped with the same type of impurities, so that the junctionless semiconductor device does not include a PN junction between the source and the body or between the body and the drain. As a result, a leakage current caused by GIDL is reduced so that operation characteristics of the semiconductor device are improved and the size of a current-flowing region is increased, resulting in an increased operation current.

Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.

Abstract: A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation film; a gate electrode filled in the active region; a bit line contact structure coupled to an active region between the gate electrodes; and a line-type bit line electrode formed over the bitline contact structure. The bit line contact structure includes a bit line contact formed over the active region; and an ohmic contact layer formed over the bit line contact.

Abstract: A semiconductor device includes junction regions formed in upper portions of both sidewalls of a trench formed in a semiconductor substrate, a first gate electrode buried in the trench and having a stepped upper surface, and a second gate electrode formed on the first gate electrode to overlap a junction region.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.

Abstract: A semiconductor device includes: a first active region defined by a recess contained in a device isolation film of a semiconductor substrate belonging to a first region and a second region, in a peripheral region including the first region, the second region, and a third region; a second active region defined by the device isolation film contained in the semiconductor substrate of the third region; a buried metal layer buried in the recess; a first conductive layer formed over the semiconductor substrate of the first region; and a second conductive layer formed over the semiconductor substrate of the second region, wherein the first conductive layer or the second conductive layer is formed over the semiconductor substrate of the third region. A three-dimensional dual gate is formed in a peripheral region, such that performance or throughput of transistors is maximized even in the peripheral region.

Abstract: A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.

Abstract: A vertical semiconductor device having a vertical channel region is disclosed. The vertical semiconductor device includes a pillar having a vertical channel region, a bit line buried in a semiconductor substrate located at a lower part of the pillar, and a body connection unit configured to couple at least one sidewall of the pillar to the semiconductor substrate. As a result, the floating body effect of the vertical semiconductor device can be more effectively removed.