Abstract: An electric compressor, including: a housing; a compression unit provided in the housing; a motor unit provided in the housing to drive the compression unit; and an inverter unit coupled to one side of the housing and controlling the motor unit, and the inverter unit includes: a support body disposed on one side of the housing; and an inverter cover coupled to one side of the support body; and the support body includes: a center part allowing a circuit board to be seated thereon; and a first receiving part extending from the center part toward a radially outer side of the center part, and having a noise reduction element disposed therein.

Abstract: An image processing apparatus and method are provided. The image processing method may generate a mask for preventing a virtual light source from being sampled on an area of a current image frame based on virtual light source information of a previous image frame, applying the mask to the current image frame, sampling the virtual light source in the current image frame to which the mask is applied, and rendering the current image frame based on the virtual light source sampled in the current image frame.

Abstract: A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

Abstract: A semiconductor device includes a substrate having a cell region and a circuit region, an upper wiring layer on the substrate, and a redistribution wiring layer on the upper wiring layer. The upper wiring layer includes a secondary uppermost wiring in the circuit region and an uppermost wiring on the secondary uppermost wiring. The uppermost wiring includes an uppermost chip pad electrically connected to the secondary uppermost wiring. At least a portion of the uppermost chip pad in the cell region. The redistribution wiring layer includes a redistribution wiring electrically connected to the uppermost chip pad. At least a portion of the redistribution wiring serving as a landing pad connected to an external connector.

Abstract: A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.

Abstract: A generator of an image processing apparatus may generate a light transport map (LTM) by sampling depth information from a light to an object based on a transparency of the object, wherein the LTM may be used to compute a visibility of the light with respect to a first point to be rendered.

Abstract: Disclosed is a method and apparatus for encoding a three-dimensional (3D) mesh. The method for encoding the 3D mesh includes determining a priority of a gate configuring a 3D mesh corresponding to a 3D object, removing vertices configuring the 3D mesh using the determined priority of the gate, and simplifying the 3D mesh.

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Abstract: A sampler of an image processing apparatus may sample at least one first virtual point light (VPL) from a direct light view. The sampler may sample a second VPL in a three-dimensional (3D) space independent of the direct light view. A calculator may calculate a luminance of the second VPL using a first VPL adjacent to the second VPL selected from among the at least one first VPL.

Abstract: Provided is an image processing apparatus for performing photon mapping, and the image processing apparatus may perform ray tracing for photon mapping, sample a ray space based on a result of the ray tracing, and perform pseudo photon mapping using the sampled ray space.

Abstract: A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.

Abstract: An apparatus and method for encoding a 3D mesh, and an apparatus and method for decoding the 3D mesh are disclosed. The 3D mesh encoding apparatus may determine mesh information including position information of each of vertices constituting the 3D mesh, and connectivity information among the vertices, based on a level, and may progressively encode the determined mesh information based on the level, thereby reducing an error with an original 3D object when compared to an equal transmission rating.

Abstract: An apparatus and method for forming a light field image includes projecting vertices of a graphic object to a far plane corresponding to a first distance directed to a screen reproducing a light field, and forming the light field image with respect to the graphic object using the vertices projected to the far plane.

Abstract: An apparatus for generating a 3D ultrasonic color image of a fetus based on skin color of a mother includes a sample image acquisition unit acquiring a sample image by photographing a skin of a pregnant woman, a 2D color map generator generating a 2D color map based on the sample image, a probe irradiating ultrasonic signals into the pregnant woman and receiving reflected ultrasonic echo signals, a volume data generator generating 3D volume data based on the ultrasonic echo signals, and a controller generating a 3D ultrasonic color image of the fetus by applying values of the 2D color map to a 3D ultrasonic image obtained by volume rendering of the 3D volume data.

Abstract: Disclosed is a three-dimensional (3D) mesh compression apparatus and method. The 3D mesh compression apparatus may generate a base mesh through a mesh simplification, may separately compress the base mesh and vertices eliminated by the simplification, and may compress 3D mesh data based on the covariance matrix.

Abstract: Provided is an apparatus and method of multi-view rendering. A method of multi-view rendering includes rendering one or more 3D objects based on a first viewpoint, transforming pixel values of pixels of the first viewpoint, which are obtained by the rendering of the 3D objects, into pixel values of pixels based on a second viewpoint that is different from the first viewpoint, detecting an occlusion region that is a remaining region other than a region represented by the pixel values obtained by the transforming of the pixel values in an image based on the second viewpoint, and rendering the detected occlusion region based on the second viewpoint.

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Abstract: An image processing apparatus and method are provided. The image processing method may generate a mask for preventing a virtual light source from being sampled on an area of a current image frame based on virtual light source information of a previous image frame, applying the mask to the current image frame, sampling the virtual light source in the current image frame to which the mask is applied, and rendering the current image frame based on the virtual light source sampled in the current image frame.

Abstract: A scalable three-dimensional (3D) mesh encoding method includes dividing the 3D mesh into layers of complexity into a plurality of graduated levels and generating vertex position information and connectivity information of each of the plurality of levels. The vertex position information about the 3D mesh is encoded based on a weighting in each bit plane and vertex position information having a higher weighting in each bit plane is first encoded.

Abstract: An integrated circuit comprising an output driver including an output terminal, and a receiving circuit including a termination resistor connected between the output terminal and a ground. The output driver comprising a first NMOS transistor configured to pull up a voltage of the output terminal to a pull-up voltage in response to a pull-up signal, and a second NMOS transistor configured to pull down the output terminal to a ground voltage in response to a pull-down signal.