Abstract: A duty cycle correction circuit includes a duty correction circuit, an information generation circuit and a duty control circuit. The duty correction circuit corrects a duty rate of an input clock signal based on a duty control code to generate an output clock signal. The information generation circuit compares a difference between operation power voltages based on an operation mode to generate voltage information. The duty control circuit receives the voltage information from the information generation circuit and generates the duty control code that includes the voltage information based on a duty rate of the output clock signal.

Abstract: A method according to an embodiment is for recovering a valuable metal from a waste electrode material of a lithium secondary battery by using lithium carbonate. An anode-cathode mixed electrode material that has been separated by draining, crushing, screening, and sorting a waste lithium secondary battery is preprocessed. A precipitation operation performed by adding lithium carbonate (Li2CO3) to a metal melt acquired by performing sulfuric acid dissolution using sulfuric acid. A valuable metal such as nickel, cobalt, manganese, aluminum, and copper is recovered as a residue in the form of a carbonate composite, and a lithium sulfate (Li2SO4) aqueous solution including lithium is recovered as a filtrate.

Abstract: The present invention relates to a composition for preventing or treating a bone disease, obesity or an obesity-mediated metabolic disease, cancer, or cancer metastasis, and a method of screening a drug for treating the diseases, which includes an inhibitor of transmembrane 4 L six family member 19 (TM4SF19) expression or activity.

Abstract: The pad interface circuit includes a first stack MOS transistor having a first terminal connected to a pad and a bulk connected to a first supply voltage; a second stack MOS transistor having a first terminal connected to a second terminal of the first stack MOS transistor and a second terminal, a gate terminal, and a bulk that are connected to the first supply voltage; and a voltage level sensing circuit generating a feedback voltage by using a pad voltage applied from the pad. In addition, the feedback voltage is applied to a gate terminal of the first stack MOS transistor.

Abstract: An overvoltage protection circuit includes primary and secondary clamping circuits. The primary clamping circuit is configured to sink overvoltage current from a power supply voltage node (e.g., Vdd) to a reference voltage node (e.g., Vss) in response to an overvoltage condition at the power supply voltage node. The secondary clamping circuit, which is electrically coupled to an output of the primary clamping circuit, is configured to sink additional overvoltage current from the power supply voltage node to the reference node in response to detection of a overvoltage flag at the output of the primary clamping circuit. This overvoltage flag may be represented by a transition (e.g., low-to-high or high-to-low) of a signal generated at an output of the primary clamping circuit.

Abstract: The pad interface circuit includes a first stack MOS transistor having a first terminal connected to a pad and a bulk connected to a first supply voltage; a second stack MOS transistor having a first terminal connected to a second terminal of the first stack MOS transistor and a second terminal, a gate terminal, and a bulk that are connected to the first supply voltage; and a voltage level sensing circuit generating a feedback voltage by using a pad voltage applied from the pad. In addition, the feedback voltage is applied to a gate terminal of the first stack MOS transistor.