Abstract: Semiconductor devices and methods of manufacture are provided whereby fences are formed over a substrate and III-V materials are grown over the substrate, wherein the fences block growth of the III-V materials. As such, smaller areas of the III-V materials are grown, thereby preventing stresses that occur with the growth of larger sheets.

Abstract: A method includes inspecting a wafer to find a first potential defect having a first wafer coordinate, and capturing a patch image of the first potential defect from the wafer. The patch image is compared with patterns of a wafer representation to find a first layout coordinate of a location in the wafer representation, wherein the location in the wafer representation corresponds to a location of the first potential defect in the wafer. A reference feature in the wafer representation is selected, wherein the reference feature in the wafer representation has a second layout coordinate. A coordinate difference between the first layout coordinate and the second layout coordinate is calculated. The coordinate difference is subtracted from the first wafer coordinate to calculate a second wafer coordinate of a reference feature in the wafer, wherein the reference feature in the wafer representation corresponds to the reference feature in the wafer.