Abstract: A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, a fin-shaped pattern on a first surface of the back wiring line, a field insulating film disposed on the fin-shaped pattern, a source/drain pattern on the fin-shaped pattern, a source/drain contact disposed on the source/drain pattern and connected to the source/drain pattern and a contact connecting via connecting the back wiring line and the source/drain contact, and is in contact with the back wiring line. The contact connecting via includes a first surface connected to the source/drain contact, and a second surface contacted to the back wiring line. A height from a second surface of the back wiring line to an upper surface of the field insulating film is smaller than a height from the second surface of the back wiring line to the first surface of the contact connecting via.

Abstract: A method of automatically configurating an IP of a VPN gateway in a home network system applied to an apartment building composed of a plurality of unit spaces includes: providing a home server connected to a network, a plurality of home network devices installed for unit spaces, respectively, a VPN server installed between the home server and the home network devices, and VPN gateways individually installed for the home network devices between the home network devices and the VPN server; acquiring an IP of an individually corresponding home network device using a local packet analyzer of the VPN gateway; and creating an IP of the VPN gateway using a network setting unit of the VPN gateway, wherein the network setting unit may make a portion of the IP of the VPN gateway be the same by referring to a portion of the IP of the individually corresponding home network device.

Abstract: A home network system that is applied to an apartment building composed of a plurality of unit spaces includes a home server connected to a network, a plurality of home network devices installed for the unit spaces, respectively, and a back bone connecting the homer server and the home network devices, and further includes a VPN server additionally installed between the home server and the home network devices and VPN gateways additionally individually installed for the home network devices between the home network devices and the back bone on the network, wherein the VPN gateway each a first may bridge terminal for communication with the home network device and a first intermediate communication terminal for communication with the VPN server and the VPN server includes a second bridge terminal for communication with the home server, a second intermediate communication terminal for communication with the corresponding VPN gateways, and a back bone virtual gateway configured to perform processing in priority t

Abstract: A method of installing a home network system applied to an apartment building composed of a plurality of unit spaces includes: providing a home server connected to a network, a plurality of home network devices installed for unit spaces, respectively, a VPN server installed between the home server and the home network devices, and VPN gateways individually installed for the home network devices between the home network devices and the VPN server, wherein the VPN gateways each include a first bridge terminal for communication with a corresponding home network device, a first intermediate communication terminal for communication with the VPN server, and an operation mode alteration detector, and the first bridge terminal includes a first end communication interface and a TAP interface; directly connecting the first end communication interface and the first intermediate communication terminal of the first bridge terminal until receiving a virtual private network start signal from the VPN server or the home serve

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: A multilayer capacitor includes a body having a plurality of dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween, and further including an active region in which the first and second internal electrodes overlap each other, and upper and lower covers disposed above and below the active region, respectively; and first and second external electrodes disposed on the body to be connected to the first and second internal electrodes, respectively, wherein the upper and lower covers include barium titanate (BT, BaTiO3) and Yttria-stabilized zirconia (YSZ).

Abstract: A multilayer capacitor includes a body having a plurality of dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween, and further including an active region in which the first and second internal electrodes overlap each other, and upper and lower covers disposed above and below the active region, respectively; and first and second external electrodes disposed on the body to be connected to the first and second internal electrodes, respectively, wherein the upper and lower covers include barium titanate (BT, BaTiO3) and Yttria-stabilized zirconia (YSZ).

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.