Abstract: The present disclosure provides a water-in-oil makeup cosmetic composition containing isostearic acid, a pigment-grade powder (specifically, a pigment-grade powder coated with a lipoamino acid), an emulsifier having an HLB greater than 0 and lower than or equal to 8, and a residual amount of water, the composition having superior water resistance and cleansing properties at the same time. The water-in-oil makeup cosmetic composition of the present disclosure can be usefully used because it has superior water resistance in environments with below-neutral pH, such as tap water, sweat, etc. and is converted to have superior cleansing properties when the skin is washed with alkaline water such as soapy water.

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: A multilayer capacitor includes a body having a plurality of dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween, and further including an active region in which the first and second internal electrodes overlap each other, and upper and lower covers disposed above and below the active region, respectively; and first and second external electrodes disposed on the body to be connected to the first and second internal electrodes, respectively, wherein the upper and lower covers include barium titanate (BT, BaTiO3) and Yttria-stabilized zirconia (YSZ).

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: A multilayer capacitor includes a body having a plurality of dielectric layers and first and second internal electrodes alternately disposed with the dielectric layers interposed therebetween, and further including an active region in which the first and second internal electrodes overlap each other, and upper and lower covers disposed above and below the active region, respectively; and first and second external electrodes disposed on the body to be connected to the first and second internal electrodes, respectively, wherein the upper and lower covers include barium titanate (BT, BaTiO3) and Yttria-stabilized zirconia (YSZ).

Abstract: A ceramic electronic component includes a body, including a dielectric layer and an internal electrode. The dielectric layer includes a plurality of dielectric grains, and at least one of the plurality of dielectric grains has a core-dual shell structure having a core and a dual shell. The dual shell includes a first shell, surrounding at least a portion of the core, and a second shell, surrounding at least a portion of the first shell. The dual shell includes different types of rare earth elements R1 and R2, and R2S1/R1S1 is 0.01 or less and R2S2/R1S1 is 0.5 to 3.0, where R1S1 and R1S2 denote concentrations of R1 included in the first shell and the second shell, respectively, and R2S1 and R2S2 denote concentrations of R2 included in the first shell and the second shell, respectively.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: In some embodiments, 3-dimensional semiconductor memory device includes a semiconductor substrate extending horizontally in a first direction and a second direction crossing the first direction. A stacked memory cell array is formed on the semiconductor substrate. The memory device further includes a separation pattern including a plurality of separation lines extending in the first direction and arranged in the second direction, and dividing the stacked memory cell array into a plurality of memory cell structures extending in the first direction and arranged in the second direction. An upper insulating layer is formed above the plurality of memory cell structures and separation lines, and a passivation layer is formed above the upper insulating layer. The passivation layer includes a plurality of first regions having a first vertical thickness. A plurality of gap regions in the passivation layer are formed between the plurality of first regions.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Abstract: Methods of fabricating semiconductor devices may include forming a stopper layer, a lower hard mask layer, an intermediate hard mask layer, and an upper hard mask pattern on a substrate, forming first spacer patterns on sidewalls of the upper hard mask pattern, selectively etching the intermediate hard mask layer using the first spacer patterns as an etching mask, forming second spacer patterns on sidewalls of the etched intermediate hard mask layer, selectively etching the lower hard mask layer using the etched second spacer layer as an etching mask, forming a patterning mask pattern that exposes a cell area and covers a common source line area on the etched lower hard mask layer and the stopper layer, and selectively etching the stopper layer using the etched lower hard mask layer and the patterning mask pattern as etching masks to form stopper patterns.

Abstract: The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem.

Abstract: A method of manufacturing a multilayer ceramic capacitor includes stacking dielectric sheets on which internal electrode patterns are printed, to form a multilayer body, forming additional dielectric sheets on portions of opposite side surfaces of the multilayer body, and sintering the multilayer body to form a ceramic body in which internal electrodes are disposed. Here, the additional dielectric sheets form attachment parts on the opposite side surfaces of the ceramic body by the sintering of the multilayer body.

Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.

Abstract: In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask.