Patents by Inventor Min-wei Tsai
Min-wei Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194762Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.Type: ApplicationFiled: February 26, 2024Publication date: June 13, 2024Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240170381Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: Chun-Hsien HUANG, Peng-Fu HSU, Yu-Syuan CAI, Min-Hsiu HUNG, Chen-Yuan KAO, Ken-Yu CHANG, Chun-I TSAI, Chia-Han LAI, Chih-Wei CHANG, Ming-Hsing TSAI
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Publication number: 20240134410Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.Type: ApplicationFiled: October 24, 2022Publication date: April 25, 2024Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG, MIN-HAN TSAI
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Patent number: 11961897Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.Type: GrantFiled: January 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
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Patent number: 11955329Abstract: A method of forming a semiconductor device includes forming a first conductive feature on a bottom surface of an opening through a dielectric layer. The forming the first conductive feature leaves seeds on sidewalls of the opening. A treatment process is performed on the seeds to form treated seeds. The treated seeds are removed with a cleaning process. The cleaning process may include a rinse with deionized water. A second conductive feature is formed to fill the opening.Type: GrantFiled: April 28, 2023Date of Patent: April 9, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Wei Chang, Min-Hsiu Hung, Chun-I Tsai, Ken-Yu Chang, Yi-Ying Liu
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Publication number: 20240098953Abstract: This application discloses electromagnetic energy mitigation assemblies and automotive vehicle components comprising the electromagnetic energy mitigation assemblies. An electromagnetic energy mitigation assembly includes a first electrically conductive layer and a second electrically conductive layer. First and second permalloy layers are along respective first and second opposite sides of the first electrically conductive layer. Third and fourth permalloy layers are along respective third and fourth opposite sides of the second electrically conductive layer. An electromagnetic noise suppression layer is sandwiched between the second and third permalloy layers. An automotive vehicle component includes an electromagnetic energy mitigation assembly configured to be positioned relative to one or more batteries of an automotive vehicle for providing electromagnetic shielding for the one or more batteries. The electromagnetic energy mitigation assembly includes a first electrically conductive layer.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Inventors: Tsang-I TSAI, Yunxi SHE, Dong-Xiang LI, Jie-Sheng CHEN, Min-Wei HSU
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Patent number: 11929314Abstract: In some implementations, one or more semiconductor processing tools may form a metal cap on a metal gate. The one or more semiconductor processing tools may form one or more dielectric layers on the metal cap. The one or more semiconductor processing tools may form a recess to the metal cap within the one or more dielectric layers. The one or more semiconductor processing tools may perform a bottom-up deposition of metal material on the metal cap to form a metal plug within the recess and directly on the metal cap.Type: GrantFiled: March 12, 2021Date of Patent: March 12, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsien Huang, Peng-Fu Hsu, Yu-Syuan Cai, Min-Hsiu Hung, Chen-Yuan Kao, Ken-Yu Chang, Chun-I Tsai, Chia-Han Lai, Chih-Wei Chang, Ming-Hsing Tsai
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Publication number: 20240069299Abstract: An optical element driving mechanism includes a movable assembly, a fixed assembly, and a driving assembly. The movable assembly is configured to be connected to an optical element. The movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly in a range of motion. The optical element driving mechanism further includes a positioning assembly configured to position the movable assembly at a predetermined position relative to the fixed assembly when the driving assembly is not operating.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Inventors: Chao-Chang HU, Kuen-Wang TSAI, Liang-Ting HO, Chao-Hsi WANG, Chih-Wei WENG, He-Ling CHANG, Che-Wei CHANG, Sheng-Zong CHEN, Ko-Lun CHAO, Min-Hsiu TSAI, Shu-Shan CHEN, Jungsuck RYOO, Mao-Kuo HSU, Guan-Yu SU
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Patent number: 11916128Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench, depositing a first ferroelectric layer over the interfacial layer, removing the first ferroelectric layer from the nFET structure, depositing a metal oxide layer in each gate trench, depositing a second ferroelectric layer over the metal oxide layer, removing the second ferroelectric layer from the pFET structure, and depositing a gate electrode in each gate trench.Type: GrantFiled: February 27, 2023Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 8847869Abstract: A liquid crystal display device and a method for driving the same are disclosed. The liquid crystal display device includes a liquid crystal panel, a gate driver unit, a clock generator, and a temperature compensation unit. The liquid crystal panel includes a pixel array. The gate driver unit is utilized for generating a plurality of driving signals to drive the pixel unit. The clock generator is electrically coupled to the gate driver unit. The temperature compensation unit is electrically coupled to the gate driver unit and the clock generator. The temperature compensation unit is utilized for adjusting an output of the clock generator to compensate the driving signals of the gate driver unit according to a temperature variance.Type: GrantFiled: December 30, 2010Date of Patent: September 30, 2014Assignee: Chunghwa Picture Tubes, Ltd.Inventors: Chun-cheng Hou, Yi-chiang Lai, Min-wei Tsai
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Publication number: 20120098814Abstract: A liquid crystal display device and a method for driving the same are disclosed. The liquid crystal display device includes a liquid crystal panel, a gate driver unit, a clock generator, and a temperature compensation unit. The liquid crystal panel includes a pixel array. The gate driver unit is utilized for generating a plurality of driving signals to drive the pixel unit. The clock generator is electrically coupled to the gate driver unit. The temperature compensation unit is electrically coupled to the gate driver unit and the clock generator. The temperature compensation unit is utilized for adjusting an output of the clock generator to compensate the driving signals of the gate driver unit according to a temperature variance.Type: ApplicationFiled: December 30, 2010Publication date: April 26, 2012Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventors: CHUN-CHENG HOU, Yi-chiang Lai, Min-wei Tsai
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Publication number: 20120098815Abstract: A liquid crystal display device and a method for driving the same are disclosed. The liquid crystal display device includes a liquid crystal panel, a gate driver unit, a clock generator, and a temperature compensation unit. The liquid crystal panel includes a pixel array. The gate driver unit is utilized for generating a plurality of driving signals to drive the pixel unit. The clock generator is electrically coupled to the gate driver unit. The temperature compensation unit is electrically coupled to the gate driver unit and the clock generator. The temperature compensation unit is utilized for adjusting an output of the clock generator to compensate the driving signals of the gate driver unit according to a temperature variance.Type: ApplicationFiled: December 30, 2010Publication date: April 26, 2012Applicant: CHUNGHWA PICTURE TUBES, LTD.Inventors: CHUN-CHENG HOU, Yi-chiang Lai, Min-wei Tsai