Patents by Inventor Min-Wk Hwang

Min-Wk Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8883622
    Abstract: A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.
    Type: Grant
    Filed: March 7, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-mo Park, Min-wk Hwang, Hyun-chul Kim
  • Publication number: 20120231619
    Abstract: A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Won-mo Park, Min-wk Hwang, Hyun-chul Kim
  • Publication number: 20070273002
    Abstract: An integrated circuit device is provided with a plurality of normally open fuse elements. A fuse element includes a fuse insulation film lining a sidewall and a bottom of a recess in a semiconductor substrate. A semiconductor fuse region of first conductivity type (e.g., N-type) is provided in the semiconductor substrate. The semiconductor fuse region extends to the sidewall of the recess. A fuse conductor is provided on a portion of the fuse insulation film extending opposite the semiconductor fuse region. A voltage induced rupture in the fuse insulation film results in a direct electrical connection between the fuse conductor and the semiconductor fuse region.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 29, 2007
    Inventor: Min-Wk Hwang
  • Patent number: 6417097
    Abstract: A method of forming a contact structure in a semiconductor device includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole. The pad contact hole is filled with a conductive pad. Thermal oxidation annealing is then carried out to form an oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: July 9, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-Wk Hwang, Jun-Yong Noh
  • Publication number: 20020025669
    Abstract: A method of forming a contact structure in a semiconductor device includes forming an interlayer insulating layer containing impurities on a semiconductor substrate. The interlayer insulating layer is patterned to form a pad contact hole. The pad contact hole is filled with a conductive pad. Thermal oxidation annealing is then carried out to form an oxide layer on a top surface of the conductive pad and at an interface between the conductive pad and the interlayer insulating layer.
    Type: Application
    Filed: January 5, 2001
    Publication date: February 28, 2002
    Inventors: Min-Wk Hwang, Jun-Yong Noh
  • Patent number: 5786265
    Abstract: Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by implanting first conductivity type impurities at a first dose level into a face of a semiconductor substrate and then forming respective field oxide isolation regions at the locations where the first channel-stop isolation regions have been implanted. A conductive layer, which contacts active regions of the substrate and covers the field oxide isolation regions, is then patterned over the field oxide isolation regions to expose central portions of the upper surfaces of the field oxide isolation regions.
    Type: Grant
    Filed: May 9, 1996
    Date of Patent: July 28, 1998
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min-wk Hwang, Hung-mo Yang, Jae-ho Kim, Won-taek Choi, Won-cheol Hong