Patents by Inventor Min-Yao CHEN

Min-Yao CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240282590
    Abstract: A package substrate is provided, in which a first circuit structure and a second circuit structure with the same specification are formed on opposite sides of a core board body, respectively, and a wiring structure of another specification is formed on the first circuit structure. In addition, the number of wiring layers of the second circuit structure is greater than the number of wiring layers of the first circuit structure to form an asymmetric package substrate. Therefore, by configuration of the wiring structure, the problem of warpage caused by uneven stress can be prevented from occurring to the package substrate.
    Type: Application
    Filed: February 15, 2024
    Publication date: August 22, 2024
    Applicant: AaltoSemi Inc.
    Inventors: Min-Yao Chen, Andrew C. Chang
  • Publication number: 20240282683
    Abstract: A package substrate is provided, in which a second dielectric layer with a smaller CTE and a third dielectric layer with a larger CTE are formed on two opposite sides of a wiring structure including a first dielectric layer, respectively, so as to avoid too large a difference in CTE of the wiring structure between two sides thereof, thereby preventing warpage from occurring to the package substrate.
    Type: Application
    Filed: February 15, 2024
    Publication date: August 22, 2024
    Applicant: AaltoSemi Inc.
    Inventors: Yin-Ju CHEN, Shi-Wei LV, Min-Yao CHEN, Andrew C. CHANG
  • Publication number: 20240266209
    Abstract: A semiconductor device includes a fin extending from a substrate and including a first fin end, a separation structure separating the first fin end from an adjacent fin end of another fin, a dummy gate spacer along sidewalls of the separation structure and the fin, a first epitaxial source/drain region in the fin and adjacent the separation structure, and a residue of a dummy gate material in a corner region between the dummy gate spacer and the first fin end. The first fin end protrudes from the dummy gate spacer into the separation structure. The residue of the dummy gate material separates the first epitaxial source/drain region from the separation structure and is triangle shaped.
    Type: Application
    Filed: February 3, 2023
    Publication date: August 8, 2024
    Inventors: Chih-Han LIN, Kuei-Yu KAO, Shih-Yao LIN, Ke-Chia TSENG, Min Chiao LIN, Hsien-Chung HUANG, Chun-Hung CHEN, Guan Kai HUANG, Chao-Cheng CHEN, Chen-Ping CHEN, Ming-Ching CHANG
  • Publication number: 20240243048
    Abstract: An electronic package is provided, in which one of insulating layers inside a package substrate is made of an Ajinomoto build-up film (ABF) material to facilitate the production of circuit structures using a redistribution layer (RDL) process, so that a circuit layer can meet the needs of high-density fine lines/fine spacing.
    Type: Application
    Filed: January 17, 2024
    Publication date: July 18, 2024
    Inventors: Andrew C. Chang, Min-Yao Chen, Yin-Ju Chen
  • Publication number: 20240213137
    Abstract: A package substrate is provided, in which a first circuit structure is formed on a core board body, and a second circuit structure is formed on the first circuit structure. A second insulating layer of the second circuit structure is made of an ABF material that is different from a material forming a first insulating layer of the first circuit structure, so that a second circuit layer with fine lines/spaces can be formed by the ABF material of the second insulating layer to achieve a purpose of multi-layer fine lines.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 27, 2024
    Inventors: Andrew C. Chang, Min-Yao Chen, Yin-Ju Chen
  • Patent number: 11997798
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: May 28, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
  • Publication number: 20240096776
    Abstract: A package substrate is provided and includes a core board body and a first circuit structure and a second circuit structure disposed on opposite sides of the core board body, where the number of wiring layers of the second circuit structure is different from the number of wiring layers of the first circuit structure, so that the package substrate is asymmetrical. The first circuit structure and the second circuit structure are designed according to the thickness and coefficient of thermal expansion of the first dielectric layer of the first circuit structure and the second dielectric layer of the second circuit structure, so as to prevent the problem of warping from occurring to the package substrate.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 21, 2024
    Inventors: Andrew C. CHANG, Min-Yao CHEN, Sung-Kun LIN
  • Publication number: 20240096721
    Abstract: An electronic package of which the manufacturing method is to dispose an electronic element on a circuit portion, encapsulate the electronic element with an Ajinomoto build-up film (ABF) used as an encapsulating layer, form a wiring layer on the encapsulating layer, and form a conductive via in the encapsulating layer. Therefore, the wiring layer can be well bonded onto the encapsulating layer as the ABF material is used as the encapsulating layer.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Inventors: Chien-Kuang LAI, Andrew C. CHANG, Min-Yao CHEN
  • Publication number: 20240021438
    Abstract: A manufacturing method of a package substrate is provided, the manufacturing method includes forming a first circuit layer on a first metal layer; forming a dielectric layer on the first metal layer and the first circuit layer; forming a second metal layer on the dielectric layer; forming a plurality of conductive blind vias in the dielectric layer and forming a second circuit layer on the second metal layer, where the plurality of conductive blind vias are electrically connected to the first circuit layer and the second circuit layer; and removing the first metal layer and a portion of the second metal layer simultaneously. Therefore, in the manufacturing method, the first metal layer and the second metal layer can be removed by one etching process, such that the time for manufacturing the package substrate can be greatly reduced to increase production quantity.
    Type: Application
    Filed: May 17, 2023
    Publication date: January 18, 2024
    Inventors: Andrew C. CHANG, Min-Yao CHEN, Sung-Kun LIN
  • Publication number: 20230298986
    Abstract: A package substrate and the manufacturing method thereof are provided. The method includes encapsulating a circuit layer and a conductive pillar on the circuit layer with an insulating layer, and then forming a groove in the insulating layer corresponding to the conductive pillar, so as to form a routing layer in the groove, so there is no need for drilling to make blind vias. Therefore, the alignment problem of conventional circuits and conductive blind vias can be avoided.
    Type: Application
    Filed: March 8, 2023
    Publication date: September 21, 2023
    Inventors: Min-Yao CHEN, Sung-Kun LIN, Andrew C. CHANG
  • Publication number: 20230290744
    Abstract: An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 14, 2023
    Inventors: Min-Yao CHEN, Andrew C. CHANG
  • Publication number: 20230282556
    Abstract: A substrate structure is provided, in which an insulator encapsulates a conductive pillar that is a single solid pillar body, and at least one wiring layer electrically connected to the conductive pillar is arranged on the insulator. Therefore, the conductive pillar is designed as a single solid pillar body to meet the requirements of thin lines, fine spacing and high-density contacts.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 7, 2023
    Inventors: Min-Yao CHEN, Pei-Ching LI, Andrew C. CHANG
  • Publication number: 20220418115
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 29, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
  • Publication number: 20220285282
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Application
    Filed: May 24, 2022
    Publication date: September 8, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Min-Yao CHEN
  • Patent number: 11432406
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 30, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Hsing Kuo Tien, Chih-Cheng Lee, Min-Yao Chen
  • Patent number: 11342272
    Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 24, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Min-Yao Chen
  • Publication number: 20220157745
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Application
    Filed: January 31, 2022
    Publication date: May 19, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Chih-Cheng LEE, Min-Yao CHEN, Hsing Kuo TIEN
  • Patent number: 11335650
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: May 17, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien
  • Publication number: 20220095462
    Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 24, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wu Chou HSU, Hsing Kuo TIEN, Chih-Cheng LEE, Min-Yao CHEN
  • Patent number: 11239184
    Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: February 1, 2022
    Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.
    Inventors: Wu Chou Hsu, Chih-Cheng Lee, Min-Yao Chen, Hsing Kuo Tien