Abstract: A semiconductor fabrication method includes: forming an epitaxial stack including at least one sacrificial epitaxial layer and at least one channel epitaxial layer; forming a plurality of fins in the epitaxial stack; performing tuning operations to prevent a width of the sacrificial epitaxial layer expanding beyond a width of the channel epitaxial layer during operations to form isolation features; forming the isolation features between the plurality of fins, wherein the width of the sacrificial epitaxial layer does not expand beyond the width of the channel epitaxial layer; forming a sacrificial gate stack; forming gate sidewall spacers on sidewalls of the sacrificial gate stack; forming inner spacers around the sacrificial epitaxial layer and the channel epitaxial layer; forming source/drain features; removing the sacrificial gate stack and sacrificial epitaxial layer; and forming a replacement metal gate, wherein the metal gate is shielded from the source/drain features.

Abstract: An electronic package is provided, in which a cover layer is embedded in a circuit structure to form a groove, and an electronic element is disposed on the cover layer in the groove. A cladding layer encapsulates the electronic element, and an external connection structure is disposed on the circuit structure and the cladding layer. Therefore, the electronic element is embedded in the groove, such that a thickness of the electronic package can be greatly reduced to meet the requirement of thinning.

Abstract: A package substrate is provided, in which the package substrate is fabricated by using a thin core board body with a thickness of at most 20 micrometers, such that the package substrate can meet the requirement of thinning and avoid reliability problems. A method of fabricating the package substrate is also provided.

Abstract: A package substrate is provided, in which a second dielectric layer with a smaller CTE and a third dielectric layer with a larger CTE are formed on two opposite sides of a wiring structure including a first dielectric layer, respectively, so as to avoid too large a difference in CTE of the wiring structure between two sides thereof, thereby preventing warpage from occurring to the package substrate.

Abstract: A package substrate is provided, in which a first circuit structure and a second circuit structure with the same specification are formed on opposite sides of a core board body, respectively, and a wiring structure of another specification is formed on the first circuit structure. In addition, the number of wiring layers of the second circuit structure is greater than the number of wiring layers of the first circuit structure to form an asymmetric package substrate. Therefore, by configuration of the wiring structure, the problem of warpage caused by uneven stress can be prevented from occurring to the package substrate.

Abstract: An electronic package is provided, in which one of insulating layers inside a package substrate is made of an Ajinomoto build-up film (ABF) material to facilitate the production of circuit structures using a redistribution layer (RDL) process, so that a circuit layer can meet the needs of high-density fine lines/fine spacing.

Abstract: A package substrate is provided, in which a first circuit structure is formed on a core board body, and a second circuit structure is formed on the first circuit structure. A second insulating layer of the second circuit structure is made of an ABF material that is different from a material forming a first insulating layer of the first circuit structure, so that a second circuit layer with fine lines/spaces can be formed by the ABF material of the second insulating layer to achieve a purpose of multi-layer fine lines.

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Abstract: A package substrate is provided and includes a core board body and a first circuit structure and a second circuit structure disposed on opposite sides of the core board body, where the number of wiring layers of the second circuit structure is different from the number of wiring layers of the first circuit structure, so that the package substrate is asymmetrical. The first circuit structure and the second circuit structure are designed according to the thickness and coefficient of thermal expansion of the first dielectric layer of the first circuit structure and the second dielectric layer of the second circuit structure, so as to prevent the problem of warping from occurring to the package substrate.

Abstract: An electronic package of which the manufacturing method is to dispose an electronic element on a circuit portion, encapsulate the electronic element with an Ajinomoto build-up film (ABF) used as an encapsulating layer, form a wiring layer on the encapsulating layer, and form a conductive via in the encapsulating layer. Therefore, the wiring layer can be well bonded onto the encapsulating layer as the ABF material is used as the encapsulating layer.

Abstract: A manufacturing method of a package substrate is provided, the manufacturing method includes forming a first circuit layer on a first metal layer; forming a dielectric layer on the first metal layer and the first circuit layer; forming a second metal layer on the dielectric layer; forming a plurality of conductive blind vias in the dielectric layer and forming a second circuit layer on the second metal layer, where the plurality of conductive blind vias are electrically connected to the first circuit layer and the second circuit layer; and removing the first metal layer and a portion of the second metal layer simultaneously. Therefore, in the manufacturing method, the first metal layer and the second metal layer can be removed by one etching process, such that the time for manufacturing the package substrate can be greatly reduced to increase production quantity.

Abstract: A package substrate and the manufacturing method thereof are provided. The method includes encapsulating a circuit layer and a conductive pillar on the circuit layer with an insulating layer, and then forming a groove in the insulating layer corresponding to the conductive pillar, so as to form a routing layer in the groove, so there is no need for drilling to make blind vias. Therefore, the alignment problem of conventional circuits and conductive blind vias can be avoided.

Abstract: An electronic package is provided, including a package substrate in which a circuit layer and a surface treatment layer are embedded in an insulating portion, and the surface treatment layer is coupled to a top surface of the circuit layer, but is not formed on a side surface of the circuit layer. Therefore, the circuit layer can maintain the original predetermined line spacing so that it is beneficial to be designed with fine line spacing/line width.

Abstract: A substrate structure is provided, in which an insulator encapsulates a conductive pillar that is a single solid pillar body, and at least one wiring layer electrically connected to the conductive pillar is arranged on the insulator. Therefore, the conductive pillar is designed as a single solid pillar body to meet the requirements of thin lines, fine spacing and high-density contacts.

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.

Abstract: A package substrate and manufacturing method thereof are provided. The package substrate includes a substrate and an electronic component. The substrate includes a cavity. The electronic component is disposed in the cavity. The electronic component includes a first region and a second region, and an optical recognition rate of the first region is distinct from that of the second region.

Abstract: A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component.

Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate, and the electronic component includes a magnetic layer and a conductive wire. The conductive wire includes a first section embedded in the magnetic layer, and a second section connected to the first section and thinner than the first section. A first upper surface of the first section is covered by the magnetic layer, a second upper surface of the second section is lower than the first upper surface, and the magnetic layer includes a first recess disposed in the upper surface and exposing the second upper surface of the second section. The first conductive trace is in the first recess and electrically connected to the second upper surface of the second section of the conductive wire.

Abstract: The present disclosure provides a package substrate and method of manufacturing the same. The package substrate includes a substrate, an electronic component and a conductive trace. The electronic component is disposed in the substrate. The electronic component includes a conductive wire comprising an alignment mark section and a connection section, and a magnetic layer partially covering the conductive wire. The magnetic layer includes an alignment window disposed in an upper surface of the magnetic layer and exposing a first upper surface of the alignment mark section, and a recess disposed in the upper surface of the magnetic layer and exposing a second upper surface of the connection section. The conductive trace is in the recess and electrically connected to the second upper surface of the connection section of the conductive wire.