Abstract: This application provides an operational amplifier that increases the stability and settling speed of a common-mode feedback circuit. The operational amplifier includes N stages of amplifiers connected in series and M common-mode feedback circuits, where N and M are integers, N?3, and N?M>1. An ith common-mode feedback circuit in the M common-mode feedback circuits is configured to: detect a common-mode output voltage of a (j+b)th stage of amplifier, and regulate an electrical parameter of at least one of the jth stage of amplifier to the (j+b)th stage of amplifier, to stabilize the common-mode output voltage of the (j+b)th stage of amplifier. An Mth common-mode feedback circuit is configured to detect and stabilize a common-mode output voltage of an Nth stage of amplifier. Herein i, j, and b are integers, M?i?1, N?j?1, i?j, j+b?N, and b?0.

Abstract: A test method and system based on a variable combination time sequence function coverage are provided, where the method includes: constructing a variable combination time sequence function coverage structure, and using the variable combination time sequence function coverage structure as a random constraint; determining a random seed of each value range of each variable in the variable combination time sequence function coverage structure; sequentially obtaining a time point as a current time point based on a time sequence of the variable combination time sequence function coverage structure; obtaining a value segment of each variable at the current time point from the variable combination time sequence function coverage structure, to form a variable combination structure at the current time point; and for the variable combination structure at the current time point, generating a random excitation of each variable to perform testing in a current scenario.

Abstract: The present disclosure discloses a method and a system for operating a complex data packet capable of being dynamically defined, and relates to the field of chip design and verification, and software technologies. The method includes: constructing a two-dimensional data structure of a data packet based on an actual programming requirement; performing slicing processing on the two-dimensional data structure of the data packet in a slicing manner; selecting an element corresponding to a processed slice from the data packet, and performing a storage and retrieval operation on a data packet element; marking each processed slice based on the processed slice; denoting a marked slice as a segment, and performing an element access operation on the segment in the data packet by using a mark; and comparing different data packets based on marked data packets and segments.

Abstract: A test method and system based on a combination function coverage are provided, where the method includes: constructing a combination function coverage based on a verification requirement, and directly using the combination function coverage as a random constraint to generate a random excitation; setting a random seed for a value range of each variable in the combination function coverage structure; generating a value segment combination sequentially or randomly based on a total quantity of scenarios in the combination function coverage structure; generating a corresponding random excitation based on the generated value segment combination and a corresponding random seed, to perform testing in a current scenario; and repeatedly perform random excitation generation and scenario testing until testing in all scenarios is completed. Definition of a function coverage is directly used as a random constraint, so that a programming workload is greatly reduced.

Abstract: The present disclosure discloses a multi-core parallel simulation method and a platform architecture for implementing multi-core parallel simulation, and relates to the field of chip simulation technologies. The simulation method includes: dividing a chip simulation task into two parts based on design code and verification code, to obtain a design code simulation task and a verification code simulation task; separately executing the design code simulation task and the verification code simulation task on different CPU cores; and further allocating the verification code simulation task to a plurality of CPU cores for execution, and executing simulation tasks among the CPU cores in a multithreaded parallel manner. The simulation method further includes: converting design code in the design code simulation task into verification code to obtain converted verification code; and allocating the converted verification code to a new CPU core for execution.

Abstract: A hedge trimmer includes a front end device including at least a cutting assembly extending along a longitudinal axis and a front housing for supporting the cutting assembly; a rear end device including at least a motor for driving the cutting assembly and a rear housing for supporting the motor; a connecting rod connecting the front end device to the rear end device; a power device supported by the rear housing and configured to supply electrical energy to the motor; a main handle connected to a first switch; and a second switch disposed on a front side of the first switch. In a direction of the longitudinal axis, the distance between the first switch and a first cutting tooth of the cutting assembly is greater than or equal to 120 mm and less than or equal to 1000 mm.

Abstract: The present disclosure discloses an SoC chip distributed simulation and verification platform and a method, and the present disclosure relates to the field of chip verification technologies. The distributed simulation and verification platform includes component modules of an SoC chip; each module has its own verification platform, and each verification platform separately runs in a different simulation process; and virtual connections between the modules are implemented through respective verification platforms, to implement system function simulation and verification. In the present disclosure, a virtual connection technology is used to connect Testbench test platforms of the modules or IPs, to implement virtual integration of the modules or IPs, thereby completing distributed simulation and verification of a system function of the SoC chip.

Abstract: This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has the advantages of having a simple structure and consuming less. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes a first start-up transistor and a second start-up transistor. A source of the first start-up transistor and a source of the second start-up transistor are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor and a gate of the second start-up transistor are configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor and a drain of the second start-up transistor are connected to input terminals of a second-stage or higher-stage amplifier.

Abstract: A circuit includes a polar transmitter to generate a radio frequency output from amplitude and phase signal components. The polar transmitter includes an amplifier to combine amplitude and phase signal components. A processor is coupled to the polar transmitter to provide the amplitude and phase signal components. The processor includes: a digital modulation circuit to generate a modulated digital signal including in-phase and quadrature signal components and a correction circuit to calculate and apply a complex digital offset for local oscillator feedthrough of the amplifier. The complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor.

Abstract: Provided are an air exhausting device for kitchenware, a dishwasher, and kitchenware. The air exhausting device for kitchenware includes: an air duct including an air outlet end and a first connecting portion disposed on the air outlet end; and an air outlet member including an air inlet end and a second connecting portion provided on the air inlet end, and an air outlet end of the air outlet member being provided with an air outlet port. The first connecting portion is slidably coupled to the second connecting portion for adjusting a relative position of the air outlet port and the air duct.

Abstract: In various implementations, systems and methods of an online gaming platform may include an audit module for corroborating fair gameplay. In some implementations, the online gaming platform can be integrated with one or more cryptocurrency exchanges to facilitate cryptocurrency transactions as well as other currency transactions. In some implementations, the cryptocurrency exchanges can be integrated with an online gaming platform that offer games, such as poker and blackjack games, enabling that the games can be played with any one or more cryptocurrencies. In some implementations, the players can pay for gameplay directly from one or more crypto currency exchange account. In some implementations, players can verify that the gameplay in the online gaming platform was fair.

Abstract: Various system and method of online gaming platform comprise a random number engine where cryptography and blockchain ledgers are utilized to generate random numbers. The random numbers can be utilized in the play of online wagering games. The online gaming platform is further integrated with a cryptocurrency exchange or transactions such that the games are played with any cryptocurrency and/or fiat currency seamlessly. The players play the games directly from a crypto exchange account.

Abstract: A circuit includes a polar transmitter to generate a radio frequency output from amplitude and phase signal components. The polar transmitter includes an amplifier to combine amplitude and phase signal components. A processor is coupled to the polar transmitter to provide the amplitude and phase signal components. The processor includes: a digital modulation circuit to generate a modulated digital signal including in-phase and quadrature signal components and a correction circuit to calculate and apply a complex digital offset for local oscillator feedthrough of the amplifier. The complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor.

Abstract: In various implementations, systems and methods of an online gaming platform may include an audit module for corroborating fair gameplay. In some implementations, the online gaming platform can be integrated with one or more cryptocurrency exchanges to facilitate cryptocurrency transactions as well as other currency transactions. In some implementations, the cryptocurrency exchanges can be integrated with an online gaming platform that offer games, such as poker and blackjack games, enabling that the games can be played with any one or more cryptocurrencies. In some implementations, the players can pay for gameplay directly from one or more crypto currency exchange account. In some implementations, players can verify that the gameplay in the online gaming platform was fair.

Abstract: A radio frequency transmitter includes a digital-to-analog converter, an analog baseband processor, and a modulator. The digital-to-analog converter is configured to convert a digital frequency-converted signal into a first analog signal, where the digital frequency-converted signal is obtained by performing digital frequency conversion on a digital baseband signal based on a first frequency signal; the analog baseband processor is configured to perform filtering and gain adjustment on the first analog signal to obtain a second analog signal; and the modulator is configured to perform up conversion based on a second frequency signal and the second analog signal, to obtain a radio frequency signal, where the second frequency signal is determined based on a local frequency signal and the first frequency signal.

Abstract: A circuit includes a polar transmitter to generate a radio frequency output from amplitude and phase signal components. The polar transmitter includes an amplifier to combine amplitude and phase signal components. A processor is coupled to the polar transmitter to provide the amplitude and phase signal components. The processor includes: a digital modulation circuit to generate a modulated digital signal including in-phase and quadrature signal components and a correction circuit to calculate and apply a complex digital offset for local oscillator feedthrough of the amplifier. The complex digital offset includes an in-phase offset correction factor and a quadrature offset correction factor.

Abstract: Various system and method of online gaming platform comprise a random number engine where cryptography and blockchain ledgers are utilized to generate random numbers. The random numbers can be utilized in the play of online wagering games. The online gaming platform is further integrated with a cryptocurrency exchange or transactions such that the games are played with any cryptocurrency and/or fiat currency seamlessly. The players play the games directly from a crypto exchange account.

Abstract: This application provides an operational amplifier that increases the stability and settling speed of a common-mode feedback circuit. The operational amplifier includes N stages of amplifiers connected in series and M common-mode feedback circuits, where N and M are integers, N?3, and N?M>1. An ith common-mode feedback circuit in the M common-mode feedback circuits is configured to: detect a common-mode output voltage of a (j+b)th stage of amplifier, and regulate an electrical parameter of at least one of the jth stage of amplifier to the (j+b)th stage of amplifier, to stabilize the common-mode output voltage of the (j+b)th stage of amplifier. An Mth common-mode feedback circuit is configured to detect and stabilize a common-mode output voltage of an Nth stage of amplifier. Herein i, j, and b are integers, M?i?1, N?j?1, i?j, j+b?N, and b?0.

Abstract: This application provides an operational amplifier and a start-up circuit of the operational amplifier. The start-up circuit has advantages of simple structure and low power consumption. The operational amplifier includes a multi-stage amplifier and a start-up circuit, where the start-up circuit includes: a first start-up transistor M16 and a second start-up transistor M17, a source of the first start-up transistor M16 and a source of the second start-up transistor M17 are connected to a tail bias node of a first-stage amplifier in the multi-stage amplifier, a gate of the first start-up transistor M16 and a gate of the second start-up transistor M17 are configured to connect to a first bias voltage Vb, and a drain of the first start-up transistor M16 and a drain of the second start-up transistor M17 are connected to input terminals of a second-stage or higher-stage amplifier.

Abstract: The present invention discloses a radio frequency receiver and a receiving method, where the method includes: performing band splitting on a radio frequency signal of multiple carriers to obtain at least one band signal, and outputting the signal; separately performing filtering and amplification processing on the at least one band signal to obtain at least one processed signal; generating multiple oscillation signals; and selectively receiving a processed signal, of the at least one processed signal, that includes a target carrier; receiving an oscillation signal corresponding to the target carrier; selectively selecting a frequency division ratio from multiple frequency division ratios; using the frequency division ratio to perform frequency division on the received oscillation signal to obtain a local oscillator signal; using the local oscillator signal to perform frequency mixing on the received processed signal that includes the target carrier to obtain a mixed signal.