Abstract: Systems, apparatus and methods for handling verification violations are disclosed. In one aspect, a method stores a list of fix information in addition to geometric shapes for each layer during verification, such as design rule checking For each primitive operation step performed during verification, two tasks are performed. First, if the primitive operation is a dimensional checking operation (i.e., width, spacing or enclosure), then for each violation, the first task creates fix information containing violation edge pairs and adds the created fix information to the fix information list on the output layer. Second, for all operations and after the output shapes on the output layer are generated, a second task passes the fix information on input layers which overlap any output shape of the output layer to the output layer's fix information list. Finally, fix guides for the final violation results are generated and drawn based on the final fix information list.

Abstract: Systems, apparatus and methods for handling verification violations are disclosed. In one aspect, a method stores a list of fix information in addition to geometric shapes for each layer during verification, such as design rule checking For each primitive operation step performed during verification, two tasks are performed. First, if the primitive operation is a dimensional checking operation (i.e., width, spacing or enclosure), then for each violation, the first task creates fix information containing violation edge pairs and adds the created fix information to the fix information list on the output layer. Second, for all operations and after the output shapes on the output layer are generated, a second task passes the fix information on input layers which overlap any output shape of the output layer to the output layer's fix information list. Finally, fix guides for the final violation results are generated and drawn based on the final fix information list.

Abstract: A computer-implemented method to perform context-sensitive incremental design rule checking (DRC) for an integrated circuit (IC). An incremental DRC engine checks design rule violations between a set of environment shapes and a set of active shapes. If no design rule violations are found, the set of active shapes will be added into the set of environment shapes. Furthermore, the incremental DRC engine can be embedded into placement tools, routing tools, or interactive layout editing tools to check design rule violations and help generate DRC error free layouts.