Abstract: A bonding apparatus and a bonding method, the bonding apparatus includes at least one first bonding device, at least two second bonding devices and a transferring device. The first bonding device is configured to visually align and bond an optically clear adhesive and a first component, to form a first bonding component. The transferring device is configured to transfer the first bonding component to the second bonding device. The second bonding device is configured to visually align and bond the first bonding component and a second component, to form a second bonding component.

Abstract: A semiconductor device may include a decoder for decoding a plurality of internal command signals and outputting a first Y-address enabling signal; a Y-address enabling signal generator for receiving the first Y-address enabling signal and outputting a second Y-address enabling signal having a predetermined enabled period; a multiplexer (MUX) for receiving the first Y-address enabling signal and the second Y-address enabling signal and selectively outputting any one thereof as a Y-address enabling signal; and a MUX controller for controlling the MUX such that the MUX selects any one of the first Y-address enabling signal or second Y-address enabling signal according to an operation mode of the semiconductor device.

Abstract: The present invention relates to a duty cycle correction circuit of a DLL circuit. According to the present invention, in an APDM, a voltage comparator of a duty cycle correction circuit operates without being reset. Therefore, although an internal power supply voltage is instantly changed in the APDM, the duty cycle of a DLL clock can be accurately set to 50%.

Abstract: A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal regardless of change in process and external conditions by selectively using a self-generated pulse signal and a pulse signal generated by an external clock signal. The column selection signal generator comprises a command combination unit, a pulse generating unit, a comparison unit and a selection unit.

Abstract: A memory device and a test method thereof enable verification of fail of a cell region by intercepting bit lines connected to the cell region in a write-verify-read test. The memory device comprises a plurality of bit line switches and a separation control unit. The bit line switches connect the bit lines of the bit line sense amplifier to those of the selected cell array in response to a bit line separation control signal in a normal mode, separate the bit lines of the bit line sense amplifier from those of the unselected cell array, and separate the bit lines of the bit line sense amplifier from those of the cell array in response to the bit line separation control signal in a test mode. The separation control unit disables the bit line separation control signal in response to a test mode signal in the test mode.

Abstract: Disclosed herein is a novel gene which is isolated from Arabidopsis thaliana and shows senescence-specific expression. The expression of the gene is under the regulation of a promoter which is also disclosed herein. The gene in combination with the promoter can be utilized at the molecular level to control plant senescence in an environmentally friendly manner.

Abstract: Compounds and methods of modulating the activity of P-glycoproteins are disclosed. The method utilizes compounds derived from Erythroxylum pervillei. The compounds overcome multidrug resistance and can be used therapeutically to enhance performance of therapeutic drugs, like chemotherapeutic drugs and antibiotics.

Abstract: The disclosed is a memory such DRAM (dynamic random access memory), particularly an X-address extractor, an X-address extraction method and a memory adaptable to a high speed operation. A DRAM receives X and Y-addresses through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address abstractor performs a function of extracting the X-address from the X and Y addresses transferred through the address line. A conventional X-address extractor has a problem that the X-address has a different value when a selection signal changes to logic ‘0’ from logic ‘1’ after an address signal changes to another value from an X-address. The present X-address extractor includes a selection signal generator, a delayer, a latch and an X-address switch, without the problem of the conventional art.

Abstract: The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable signal and a second bank enable signal. The present invention has an advantage that there is no problem of substantially reducing a refresh prosecution time for a second portion because a delayed refresh enable signal is being disabled even while the second bank enable signal is being enabled.

Abstract: The disclosed is a memory such DRAM (dynamic random access memory), particularly an X-address extractor, an X-address extraction method and a memory adaptable to a high speed operation. A DRAM receives X and Y-addresses through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address abstractor performs a function of extracting the X-address from the X and Y addresses transferred through the address line. A conventional X-address extractor has a problem that the X-address has a different value when a selection signal changes to logic ‘0’ from logic ‘1’ after an address signal changes to another value from an X-address. The present X-address extractor includes a selection signal generator, a delayer, a latch and an X-address switch, without the problem of the conventional art.

Abstract: We have discovered a target protein which is conserved in fungi and essential for cell viability, cell growth, the control of cell morphogenesis, and combinations thereof. An antifungal agent targets the protein in a fungus, but not an infected host. This protein is encoded by the bot1 gene in Schizosaccharomyces pombe, Saccharomyces cerevisiae, and Candida albicans but is not detected in a filamentous fungus.