Abstract: A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.

Abstract: There is provided an inkjet head including: a flow path plate having a plurality of ink chambers; a nozzle plate having a plurality of nozzles connected to the respective ink chambers in order to eject ink in the ink chambers to the outside; a piezoelectric actuator provided above the ink chambers and controlling pressure of the ink chambers; and a parylene protective film provided in order to prevent oxidization of the piezoelectric actuator.

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract: A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.

Abstract: A delay locked loop includes a DLL hold control unit that receives a first control signal and outputs a DLL hold control signal, and a DLL block that receives the DLL hold control signal and generates a DLL clock.

Abstract: A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from the first cell mat and the second cell mat in response to the row address and a refresh signal to be used in a refresh operation; and a bank controller for sequentially enabling the first cell mat and the second cell mat in response to a bank address and the refresh signal.

Abstract: A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated.

Abstract: A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.

Abstract: A semiconductor device may include a decoder for decoding a plurality of internal command signals and outputting a first Y-address enabling signal; a Y-address enabling signal generator for receiving the first Y-address enabling signal and outputting a second Y-address enabling signal having a predetermined enabled period; a multiplexer (MUX) for receiving the first Y-address enabling signal and the second Y-address enabling signal and selectively outputting any one thereof as a Y-address enabling signal; and a MUX controller for controlling the MUX such that the MUX selects any one of the first Y-address enabling signal or second Y-address enabling signal according to an operation mode of the semiconductor device.

Abstract: A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated.

Abstract: A semiconductor memory device includes: a termination resistance supply unit connected to a pad to supply termination resistances corresponding to a plurality of control signals; a decoding unit for decoding the plurality of ODT setting signals to output an ODT enable signal and a plurality of decoding output signals; a control signal generating unit for receiving the plurality of decoding output signals to output the plurality of control signals in response to an ODT off signal and a clock signal; and an output control unit for activating one of the plurality of control signals when a read enable detection signal is activated.

Abstract: A delay locked loop includes a DLL hold control unit that receives a first control signal and outputs a DLL hold control signal, and a DLL block that receives the DLL hold control signal and generates a DLL clock.

Abstract: A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from the first cell mat and the second cell mat in response to the row address and a refresh signal to be used in a refresh operation; and a bank controller for sequentially enabling the first cell mat and the second cell mat in response to a bank address and the refresh signal.

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract: A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.

Abstract: A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from the first cell mat and the second cell mat in response to the row address and a refresh signal to be used in a refresh operation; and a bank controller for sequentially enabling the first cell mat and the second cell mat in response to a bank address and the refresh signal.

Abstract: The present invention relates to a duty cycle correction circuit of a DLL circuit. According to the present invention, in an Active Power-Down Mode (APDM), a voltage comparator of a duty cycle correction circuit operates without being reset. Therefore, although an internal power supply voltage is instantly changed in the APDM, the duty cycle of a DLL clock can be accurately set to 50%.

Abstract: A semiconductor memory device includes: a termination resistance supply unit connected to a pad to supply termination resistances corresponding to a plurality of control signals; a decoding unit for decoding the plurality of ODT setting signals to output an ODT enable signal and a plurality of decoding output signals; a control signal generating unit for receiving the plurality of decoding output signals to output the plurality of control signals in response to an ODT off signal and a clock signal; and an output control unit for activating one of the plurality of control signals when a read enable detection signal is activated.

Abstract: A column selection signal generator of a semiconductor memory device is configured to maintain a predetermined pulse width of a column selection signal regardless of change in process and external conditions by selectively using a self-generated pulse signal and a pulse signal generated by an external clock signal. The column selection signal generator includes a command combination unit, a pulse generating unit, a comparison unit and a selection unit.

Abstract: A memory device and a test method thereof enable verification of failure of a cell region by intercepting bit lines connected to the cell region in a write-verify-read test. The memory device comprises a plurality of bit line switches and a separation control unit. The bit line switches connect the bit lines of the bit line sense amplifier to those of the selected cell array in response to a bit line separation control signal in a normal mode, separate the bit lines of the bit line sense amplifier from those of the unselected cell array, and separate the bit lines of the bit line sense amplifier from those of the cell array in response to the bit line separation control signal in a test mode. The separation control unit disables the bit line separation control signal in response to a test mode signal in the test mode.