Abstract: Disclosed is an adaptive interface circuit for connecting a USB interface and a PCIe interface. The adaptive interface circuit includes a UAS protocol processing circuit, a data buffer, and an NVMe protocol processing circuit. The UAS protocol processing circuit receives a UAS command from a host via the USB interface and transmits a write-ready signal to the host according to the UAS command so that the host transmits host data to the data buffer according to the write-ready signal; the UAS protocol processing circuit also provides the UAS command to the NVMe protocol processing circuit. The NVMe protocol processing circuit generates X NVMe command(s) according to the UAS command; afterwards the NVMe protocol processing circuit starts transmitting X doorbell signal(s) to a storage device via the PCIe interface so as to let the storage device retrieve the host data from the data buffer according to the X NVMe command(s).

Abstract: A smart interface circuit includes: a first protocol processing circuit receiving several first protocol commands including a first command and a second command from a first device, storing the commands in an instruction register that is accessible to a second protocol processing circuit, and outputting first data and second data stored in a data buffer to the first device according to the first command and the second command respectively; and the second protocol processing circuit generating X second protocol command(s) according to the first command to request a second device to output the first data to the data buffer, and before the first protocol processing circuit finishes outputting the first data to the first device, the second protocol processing circuit generating Y second protocol command(s) according to the second command to request the second device to output the second data to the data buffer.

Abstract: A smart interface circuit includes: a first protocol processing circuit receiving several first protocol commands including a first command and a second command from a first device, storing the commands in an instruction register that is accessible to a second protocol processing circuit, and outputting first data and second data stored in a data buffer to the first device according to the first command and the second command respectively; and the second protocol processing circuit generating X second protocol command(s) according to the first command to request a second device to output the first data to the data buffer, and before the first protocol processing circuit finishes outputting the first data to the first device, the second protocol processing circuit generating Y second protocol command(s) according to the second command to request the second device to output the second data to the data buffer.

Abstract: Disclosed is an adaptive interface circuit for connecting a USB interface and a PCIe interface. The adaptive interface circuit includes a UAS protocol processing circuit, a data buffer, and an NVMe protocol processing circuit. The UAS protocol processing circuit receives a UAS command from a host via the USB interface and transmits a write-ready signal to the host according to the UAS command so that the host transmits host data to the data buffer according to the write-ready signal; the UAS protocol processing circuit also provides the UAS command to the NVMe protocol processing circuit. The NVMe protocol processing circuit generates X NVMe command(s) according to the UAS command; afterwards the NVMe protocol processing circuit starts transmitting X doorbell signal(s) to a storage device via the PCIe interface so as to let the storage device retrieve the host data from the data buffer according to the X NVMe command(s).

Abstract: Estimation circuit for SOC and SOH of battery includes a control circuit, a current estimation circuit, an open-circuit voltage detection circuit, an optional multiplexer and an electrical-capacity calculation circuit. The control circuit operates under six modes based on a reset signal, a voltage signal and a current signal. The current estimation circuit comprises a current modification circuit and a Coulomb integral circuit, the current modification circuit receives the current signal and outputs a modifying current signal, the Coulomb integral circuit integrates the modifying current signal to obtain an estimating electrical-capacity value. The open-circuit voltage detection circuit receives the voltage signal and outputs an initial electrical-capacity value. The optional multiplexer receives an estimation optional signal, the estimating electrical-capacity value and the initial electrical-capacity value to output an estimating electrical-capacity signal.

Abstract: Estimation circuit for SOC and SOH of battery includes a control circuit, a current estimation circuit, an open-circuit voltage detection circuit, an optional multiplexer and an electrical-capacity calculation circuit. The control circuit operates under six modes based on a reset signal, a voltage signal and a current signal. The current estimation circuit comprises a current modification circuit and a Coulomb integral circuit, the current modification circuit receives the current signal and outputs a modifying current signal, the Coulomb integral circuit integrates the modifying current signal to obtain an estimating electrical-capacity value. The open-circuit voltage detection circuit receives the voltage signal and outputs an initial electrical-capacity value. The optional multiplexer receives an estimation optional signal, the estimating electrical-capacity value and the initial electrical-capacity value to output an estimating electrical-capacity signal.