Abstract: A light emitting device includes a first electrode and a second electrode, a light emitting layer between the first electrode and the second electrode, a hole transport common layer between the first electrode and the light emitting layer, and an electron transport common layer between the light emitting layer and the second electrode, a first hole transport auxiliary layer and a second hole transport auxiliary layer provided sequentially between the hole transport common layer and the light emitting layer, and an electron blocking layer between the second hole transport auxiliary layer and the light emitting layer. A highest occupied molecular orbital (HOMO) energy level of the second hole transport auxiliary layer can be higher than a HOMO energy level of the first hole transport auxiliary layer and a HOMO energy level of the electron blocking layer respectively located on opposite sides of the second hole transport auxiliary layer.

Abstract: A secondary battery including a terrace portion formed along a perimeter of an accommodation portion of an outer casing and having a sealing portion with a portion of a width thereof sealed a lead film disposed between and electrode lead and the outer casing, a gas guide portion disposed between the electrode lead and the lead film and including a permeable portion on an outer side of the sealing portion and a gas channel extending from the permeable portion toward the electrode assembly via the sealing portion. A reinforcing film on the lead film to covers a portion of the permeable portion. The reinforcing film includes an insertion portion occupying a portion of the width of the sealing portion, and the insertion portion is a region in which one end of the reinforcing film extends in an inward direction and is inserted between the outer casing and the lead film.

Abstract: A light emitting display device may include a first insulating film having recess portions and a flat portion between adjacent recess portions at first and second subpixels adjacent to each other, a first electrode in a recess portion of each of the first and second subpixels, a dummy pattern on the flat portion of the first insulating film and spaced apart from the first electrode, a first electron blocking layer at the first subpixel and a second electron blocking layer at the second subpixel, the first and second electron blocking layers having an edge on the dummy pattern and spaced apart from each other, a first color light emitting layer provided at the first subpixel and covering the edge of the first electron blocking layer, a second color light emitting layer on the second electron blocking layer, and a second electrode on the first and second color light emitting layers.

Abstract: Disclosed is a light emitting display device configured such that the construction of an electron blocking unit located adjacent to an emission layer is differently applied to subpixels having different turn-on voltages, thereby preventing current leakage and reducing power consumption, thereby improving efficiency and visual sensation of the display device.

Abstract: A display device includes: a display panel including a pixel connected to a first gate line, a second gate line, a third gate line, and a light emission control line; a gate driver; and a timing controller. The gate driver is to: output a first gate signal, a second gate signal, a third gate signal, and an emission control signal, each having a pulse, during an active period; and output the emission control signal having a pulse, while maintaining the first and second gate signals at a constant voltage, during a blank period. The timing controller is to: provide, to the gate driver during the active period, first to fourth clock signals that toggle between a logic high level and a logic low level; and maintain the first and second clock signals at a constant voltage during the blank period.

Abstract: A display device includes: a substrate; a plurality of transistors disposed on the substrate; an initialization voltage line disposed on the substrate and including a first initialization voltage line that extends in a first direction, and a second initialization voltage line that extends in a second direction; and a driving voltage line disposed on the substrate and extending in the second direction, wherein each of the first initialization voltage line and the driving voltage line is connected to at least one of the plurality of transistors, and the second initialization voltage line and the driving voltage line overlap each other.

Abstract: A light emitting device can include a first electrode and a second electrode facing each other, and an electron blocking layer, a first light emitting layer, and an electron transport layer between the first electrode and the second electrode. The first light emitting layer can include a p-type host, a first n-type host, a second n-type host, and a dopant, a LUMO energy level of the first n-type host is higher than a LUMO energy level of the second n-type host. A hole mobility of the first n-type host can be greater than a hole mobility of the second n-type host and can be smaller than a hole mobility of the p-type host.

Abstract: Discussed is a light emitting device, including a first electrode and a second electrode facing each other, an electron blocking layer, a first emission layer, and an electron transport layer between the first electrode and the second electrode. The first emission layer includes a first p-type host, a second p-type host, an n-type host, and a dopant. A HOMO energy level of the first p-type host is lower than a HOMO energy level of the second p-type host, and hole mobility of the second p-type host is greater than hole mobility of the first p-type host.

Abstract: A display device includes: a substrate; a plurality of transistors disposed on the substrate; an initialization voltage line disposed on the substrate and including a first initialization voltage line that extends in a first direction, and a second initialization voltage line that extends in a second direction; and a driving voltage line disposed on the substrate and extending in the second direction, wherein each of the first initialization voltage line and the driving voltage line is connected to at least one of the plurality of transistors, and the second initialization voltage line and the driving voltage line overlap each other.

Abstract: Provided is a composition for strengthening the dermal layer of the skin and improving skin elasticity or alleviating skin wrinkles by strengthening the basement membrane of the skin. The composition according to the presently claimed subject matter contains a compound represented by chemical formula 1; and a compound represented by chemical formula 2 and/or a compound represented by chemical formula 3, at the same time, and thus has superior skin elasticity or wrinkle alleviation effect than a composition containing the compound represented by chemical formula 1 alone, the compound represented by chemical formula 2 alone, or the compound represented by chemical formula 3 alone.

Abstract: Disclosed is a light emitting display device including a substrate on which first to third sub-pixels are provided, and first to third light emitting devices that are respectively provided in the first to third sub-pixels to emit light of different wavelengths. The first to third light emitting devices each include first to third intermediate layers between a first electrode and a second electrode that face each other. The first to third intermediate layers include a red light emitting layer, a green light emitting layer, and a blue light emitting layer in order on the first electrode, in which the blue light emitting layer of the first intermediate layer has a vertical phase higher than those of the blue light emitting layers of the second and third intermediate layers.

Abstract: Disclosed is a light emitting display device configured such that the construction of an electron blocking unit located adjacent to an emission layer is differently applied to subpixels having different turn-on voltages, thereby preventing current leakage and reducing power consumption, thereby improving efficiency and visual sensation of the display device.

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

Abstract: The present invention relates to a pouch-shaped battery cell with improved safety, and more particularly to a pouch-shaped battery cell including an electrode assembly, a cell case constituted by an upper case and a lower case configured to define a space portion configured to receive the electrode assembly, and a rupture induction portion. The electrode assembly including a negative electrode, a separator, and a positive electrode. Whereby the rapture induction portion is configured to induce rupture of the cell case when the pressure in the cell case increases is provided in the space portion of the cell case.

Abstract: A display device includes: a first substrate including a display area and a non-display area; a second substrate facing the first substrate; a sealing member disposed in the non-display area and coupling the first substrate to the second substrate; a sensing contact area disposed at an inner side of the sealing member; a sensing signal line disposed in the sensing contact area; a sensing contact pattern disposed in the sensing contact area and electrically connected to the sensing signal line; a control signal line disposed between the first substrate and the sensing signal line; and a shielding pattern disposed between the control signal line and the sensing signal line, the shielding pattern overlapping the control signal line or the sensing signal line.

Abstract: A display device includes: a substrate; a plurality of transistors disposed on the substrate; an initialization voltage line disposed on the substrate and including a first initialization voltage line that extends in a first direction, and a second initialization voltage line that extends in a second direction; and a driving voltage line disposed on the substrate and extending in the second direction, wherein each of the first initialization voltage line and the driving voltage line is connected to at least one of the plurality of transistors, and the second initialization voltage line and the driving voltage line overlap each other.

Abstract: A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.

Abstract: Present invention relates to a method of fabricating a semiconductor device that can facilitate the processes of etching a supporter and removing a mold layer. According to the present invention, a method of fabricating a semiconductor device semiconductor device comprises: sequentially forming a substructure over a substrate and a etch stop layer over the substructure; forming a stack structure of alternately stacked mold layers and supporter layers over the etch stop layer; forming a plurality of supporter holes in the stack structure exposing the etch stop layer; forming a sacrificial layer filling each of the plurality of the supporter holes; forming a plurality of lower electrode openings exposing the substructure by etching the sacrificial layer and the stack structure; and forming a lower electrode inside the plurality of lower electrode openings.

Abstract: A display device includes: a substrate; a plurality of transistors disposed on the substrate; an initialization voltage line disposed on the substrate and including a first initialization voltage line that extends in a first direction, and a second initialization voltage line that extends in a second direction; and a driving voltage line disposed on the substrate and extending in the second direction, wherein each of the first initialization voltage line and the driving voltage line is connected to at least one of the plurality of transistors, and the second initialization voltage line and the driving voltage line overlap each other.

Abstract: A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.