Patents by Inventor Mina RYO

Mina RYO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10453923
    Abstract: An interlayer insulating film is patterned, contact holes are formed, and in the contact holes, a source contact portion forming an ohmic contact with the silicon carbide body is formed. Thereafter, a titanium film and an aluminum wiring layer are continuously formed in this sequence on the interlayer insulating film and the source contact portion. At this time, the thickness of the titanium film is about 1.0 ?m or less. Thereafter, by heat treatment for curing of a passivation film or heat treatment thereafter, the titanium film and the aluminum wiring layer react, generating a TiAl alloy film between the titanium film and the aluminum wiring layer. The thickness of the TiAl alloy film, for example, is kept to about 1 nm to 100 nm; and the TiAl alloy film and the source contact portion do not contact each other.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Mina Ryo, Takuya Komatsu
  • Patent number: 10418445
    Abstract: In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Takeshi Tawara, Masaki Miyazato, Masaaki Miyajima
  • Publication number: 20180358444
    Abstract: In a vertical MOSFET having a trench gate structure, a lifetime killer region is provided in a p-type epitaxial layer formed by epitaxial growth. The lifetime killer region includes an electron lifetime killer that causes electrons entering the lifetime killer region to recombine and become extinct. As a result, the lifetime killer region decreases the electrons generated at the pn interface of the p-type epitaxial layer and an n-type drift layer and enables a configuration in which electrons are not delivered to the p-type epitaxial layer.
    Type: Application
    Filed: May 24, 2018
    Publication date: December 13, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Takeshi Tawara, Masaki Miyazato, Masaaki Miyajima
  • Patent number: 10079298
    Abstract: A semiconductor device includes on an n-type semiconductor substrate of silicon carbide, an n-type semiconductor layer, a p-type base region, an n-type source region, a p-type contact region, a gate insulating film, a gate electrode, and a source electrode. The semiconductor device has a drain electrode on a back surface of the semiconductor substrate. On a surface of the gate electrode, an interlayer insulating film is disposed. The interlayer insulating film has plural layers among which, one layer is formed by a silicon nitride film. With such a structure, degradation of semiconductor device properties are suppressed. Further, increases in the number of processes at the time of manufacturing are suppressed.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: September 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa Kinoshita, Yasuyuki Hoshi, Yuichi Harada, Yoshiyuki Sakai, Masanobu Iwaya, Mina Ryo
  • Patent number: 9856582
    Abstract: A method is disclosed with provides stable growth of SiC single crystals, particularly 4H—SiC single crystals, with an effective crystal growth rate for a prolonged time even at a low temperature range of 2000° C. or lower. A raw material containing Si, Ti and Ni is charged into a crucible made of graphite and heat-melted to obtain a solvent. At the same time, C is dissolved out from the crucible into the solvent to obtain a melt. A SiC seed crystal substrate is then brought into contact with the melt such that SiC is supersaturated in the melt in the vicinity of the surface of the SiC seed crystal substrate, thereby allowing growth and production of an SiC single crystal on the SiC seed crystal substrate.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: January 2, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Yoshiyuki Yonezawa, Takeshi Suzuki
  • Publication number: 20170271456
    Abstract: An interlayer insulating film is patterned, contact holes are formed, and in the contact holes, a source contact portion forming an ohmic contact with the silicon carbide body is formed. Thereafter, a titanium film and an aluminum wiring layer are continuously formed in this sequence on the interlayer insulating film and the source contact portion. At this time, the thickness of the titanium film is about 1.0 ?m or less. Thereafter, by heat treatment for curing of a passivation film or heat treatment thereafter, the titanium film and the aluminum wiring layer react, generating a TiAl alloy film between the titanium film and the aluminum wiring layer. The thickness of the TiAl alloy film, for example, is kept to about 1 nm to 100 nm; and the TiAl alloy film and the source contact portion do not contact each other.
    Type: Application
    Filed: February 1, 2017
    Publication date: September 21, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki OHSE, Mina RYO, Takuya KOMATSU
  • Publication number: 20160315186
    Abstract: A semiconductor device includes on an n-type semiconductor substrate of silicon carbide, an n-type semiconductor layer, a p-type base region, an n-type source region, a p-type contact region, a gate insulating film, a gate electrode, and a source electrode. The semiconductor device has a drain electrode on a back surface of the semiconductor substrate. On a surface of the gate electrode, an interlayer insulating film is disposed. The interlayer insulating film has plural layers among which, one layer is formed by a silicon nitride film. With such a structure, degradation of semiconductor device properties are suppressed. Further, increases in the number of processes at the time of manufacturing are suppressed.
    Type: Application
    Filed: July 1, 2016
    Publication date: October 27, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Akimasa KINOSHITA, Yasuyuki HOSHI, Yuichi HARADA, Yoshiyuki SAKAI, Masanobu IWAYA, Mina RYO
  • Patent number: 9281194
    Abstract: An ohmic electrode (6) of a silicon carbide semiconductor apparatus is fabricated by forming an ohmic metal film on a silicon carbide substrate (1) by sputtering a target including a mixture or an alloy having therein nickel, and a metal(s) reducing the magnetic permeability of nickel and producing a carbide, where compositional ratios of the mixture or alloy are adjusted to predetermined compositional ratios, and by executing heat treatment for the ohmic metal film to calcinate the ohmic metal film. Thus, the ohmic electrode (6) that is for the silicon carbide semiconductor apparatus and capable of improving the use efficiency of the target can be manufactured, whose film thickness is even and that does not peel off.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: March 8, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Shinichi Nakamata, Akimasa Kinoshita, Kenji Fukuda
  • Publication number: 20150194313
    Abstract: An ohmic electrode (6) of a silicon carbide semiconductor apparatus is fabricated by forming an ohmic metal film on a silicon carbide substrate (1) by sputtering a target including a mixture or an alloy having therein nickel, and a metal(s) reducing the magnetic permeability of nickel and producing a carbide, where compositional ratios of the mixture or alloy are adjusted to predetermined compositional ratios, and by executing heat treatment for the ohmic metal film to calcinate the ohmic metal film. Thus, the ohmic electrode (6) that is for the silicon carbide semiconductor apparatus and capable of improving the use efficiency of the target can be manufactured, whose film thickness is even and that does not peel off.
    Type: Application
    Filed: March 18, 2013
    Publication date: July 9, 2015
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Mina Ryo, Shinichi Nakamata, Akimasa Kinoshita, Kenji Fukuda
  • Publication number: 20120237428
    Abstract: A method is disclosed with provides stable growth of SiC single crystals, particularly 4H—SiC single crystals, with an effective crystal growth rate for a prolonged time even at a low temperature range of 2000° C. or lower. A raw material containing Si, Ti and Ni is charged into a crucible made of graphite and heat-melted to obtain a solvent. At the same time, C is dissolved out from the crucible into the solvent to obtain a melt. A SiC seed crystal substrate is then brought into contact with the melt such that SiC is supersaturated in the melt in the vicinity of the surface of the SiC seed crystal substrate, thereby allowing growth and production of an SiC single crystal on the SiC seed crystal substrate.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 20, 2012
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Mina RYO, Yoshiyuki YONEZAWA, Takeshi SUZUKI