Patents by Inventor Minakshisundaran Balasubramanian Anand
Minakshisundaran Balasubramanian Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8295295Abstract: A system and a method for automatically segmenting and merging routing domains within a network. The system includes one or more gateway devices and a plurality of nodes segmented into one or more routing domains. Each of said plurality of nodes maintains a single gateway device from among said plurality of gateway devices as the node's primary gateway at any time. Each of said gateway devices possesses a gateway color attribute. Each of said plurality of nodes maintains a node color attribute value whose value is derived from the value of said gateway color attribute of then node's primary gateway. Each node's routing domain is determined by the node's color attribute value.Type: GrantFiled: January 24, 2007Date of Patent: October 23, 2012Assignee: Cooper Technologies CompanyInventors: Timothy Clark Winter, Minakshisundaran Balasubramanian Anand, Prakash Chakravarthi
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Patent number: 8164481Abstract: A system and method for conducting bi-directional communication sessions with sensing and control devices, such as utility meters, from a mobile device. A system for conducting bi-directional communication sessions with utility meters from a mobile device includes a mobile device capable of acquiring a communication session with a meter unit connected to a utility meter, a vehicle in which the mobile device is located, and a plurality of meter units connected to a plurality of utility meters. The meter units are capable of receiving and executing commands to obtain data and perform actions on the utility meters. The actions include a peak consumption value reset of the utility meter. Each command message includes a token that enables the endpoint radio transceiver devices to determine the commanded one or more operations have been performed.Type: GrantFiled: February 27, 2008Date of Patent: April 24, 2012Assignee: Cooper Technologies CompanyInventors: Arthur John Klaus, Timothy Clark Winter, Minakshisundaran Balasubramanian Anand
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Publication number: 20080175257Abstract: A system and a method for automatically segmenting and merging routing domains within a network. The system includes one or more gateway devices and a plurality of nodes segmented into one or more routing domains. Each of said plurality of nodes maintains a single gateway device from among said plurality of gateway devices as the node's primary gateway at any time. Each of said gateway devices possesses a gateway color attribute. Each of said plurality of nodes maintains a node color attribute value whose value is derived from the value of said gateway color attribute of then node's primary gateway. Each node's routing domain is determined by the node's color attribute value.Type: ApplicationFiled: January 24, 2007Publication date: July 24, 2008Inventors: Timothy Clark Winter, Minakshisundaran Balasubramanian Anand, Prakash Chakravarthi
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Publication number: 20080150752Abstract: A system and method for conducting bi-directional communication sessions with sensing and control devices, such as utility meters, from a mobile device. A system for conducting bi-directional communication sessions with utility meters from a mobile device includes a mobile device capable of acquiring a communication session with a meter unit connected to a utility meter, a vehicle in which the mobile device is located, and a plurality of meter units connected to a plurality of utility meters. The meter units are capable of receiving and executing commands to obtain data and perform actions on the utility meters. The actions include a peak consumption value reset of the utility meter. Each command message includes a token that enables the endpoint radio transceiver devices to determine the commanded one or more operations have been performed.Type: ApplicationFiled: February 27, 2008Publication date: June 26, 2008Inventors: Arthur John Klaus, Timothy Clark Winter, Minakshisundaran Balasubramanian Anand
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Publication number: 20080117076Abstract: An system and a method for conducting bi-directional communication sessions with sensing and control devices, such as utility meters, from a mobile device. A system for conducting bi-directional communication sessions with utility meters from a mobile device includes a mobile device capable of acquiring a communication session with a meter unit connected to a utility meter, a vehicle in which the mobile device is located, and a plurality of meter units connected to a plurality of utility meters. The meter units are capable of receiving and executing commands to obtain data and perform actions on the utility meters. The actions include a peak consumption value reset of the utility meter.Type: ApplicationFiled: November 16, 2006Publication date: May 22, 2008Inventors: Arthur John Klaus, Timothy Clark Winter, Minakshisundaran Balasubramanian Anand
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Patent number: 6720658Abstract: In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.Type: GrantFiled: October 30, 2002Date of Patent: April 13, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Minakshisundaran Balasubramanian Anand
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Publication number: 20030062625Abstract: In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.Type: ApplicationFiled: October 30, 2002Publication date: April 3, 2003Applicant: Kabushiki Kaisha ToshibaInventor: Minakshisundaran Balasubramanian Anand
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Patent number: 6500748Abstract: In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.Type: GrantFiled: October 11, 2001Date of Patent: December 31, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Minakshisundaran Balasubramanian Anand
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Patent number: 6368951Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: GrantFiled: July 13, 2001Date of Patent: April 9, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Patent number: 6362528Abstract: In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.Type: GrantFiled: August 20, 1997Date of Patent: March 26, 2002Assignee: Kabushiki Kaisha ToshibaInventor: Minakshisundaran Balasubramanian Anand
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Publication number: 20020020918Abstract: In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.Type: ApplicationFiled: October 11, 2001Publication date: February 21, 2002Applicant: Kabushiki Kaisha ToshibaInventor: Minakshisundaran Balasubramanian Anand
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Publication number: 20010038147Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: ApplicationFiled: July 13, 2001Publication date: November 8, 2001Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Patent number: 6307265Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.Type: GrantFiled: August 15, 1996Date of Patent: October 23, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Minakshisundaran Balasubramanian Anand, Hideki Shibata, Masaki Yamada
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Patent number: 6306753Abstract: Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.Type: GrantFiled: March 14, 2000Date of Patent: October 23, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Minakshisundaran Balasubramanian Anand, Hideki Shibata, Masaki Yamada
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Patent number: 6291891Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.Type: GrantFiled: January 12, 1999Date of Patent: September 18, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Kazuyuki Higashi, Noriaki Matsunaga, Akihiro Kajita, Tetsuo Matsuda, Tadashi Iijima, Hisashi Kaneko, Hideki Shibata, Naofumi Nakamura, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno, Katsuya Okumura
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Patent number: 6253362Abstract: Wiring of a non-uniform density is laid out on a chip. Then, the chip is virtually divided into a plurality of sub chips. The wiring density of each sub chip is obtained to obtain the density distribution function of wiring. After that, an index indicative of variations in the density of wiring is obtained on the basis of the density distribution function, thereby determining whether or not the index falls within an allowable range. If the index is out of the allowable range, the density distribution function is repeatedly updated until the index falls within the allowable range. Dummy wiring is provided on a region obtained by subtracting a region corresponding to the initial density distribution function from a region corresponding to the last density distribution function.Type: GrantFiled: October 20, 1998Date of Patent: June 26, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Minakshisundaran Balasubramanian Anand, Hiroshi Ohtani
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Patent number: 6037247Abstract: The present invention provides a way how to use a technique for forming the contact of a diffusion layer in a self-alignment manner in combination with a salicide technique. The most important finding in the way is that when an insulating film is deposited over the entire surface, the insulating film deposited on a shared diffusion layer which is present in a depressed portion between two electrodes is thinner in a natural course of events than that deposited on open-surfaces of the two electrodes. When such an insulating film different in thickness is etched, the relatively thin insulating film formed on the shared diffusion layer is substantially completely removed, whereas the relatively thick insulating film formed on the two electrodes is not completely removed and remains as a thin film.Type: GrantFiled: February 9, 1998Date of Patent: March 14, 2000Assignee: Kabushiki Kaisha ToshibaInventor: Minakshisundaran Balasubramanian Anand
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Patent number: 5982040Abstract: A semiconductor device includes a semiconductor substrate having a main surface, and a multi-layered wiring layer formed on the main surface of the semiconductor substrate, the multi-layered wiring layer having a plurality of wiring layers insulatively laminated, wherein the melting points of the plurality of wiring layers are set gradually lower in a direction towards the higher-level side.Type: GrantFiled: November 14, 1997Date of Patent: November 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Masaki Yamada, Minakshisundaran Balasubramanian Anand, Hideki Shibata
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Patent number: 5966634Abstract: In a method of manufacturing a semiconductor device, when a copper diffusion preventing film portion on the connecting hole bottom portion is to be removed, a film thickness of other portion of the copper diffusion preventing film not to be removed is more thickly formed than that of the to-be-removed copper diffusion preventing film portion on the connecting hole bottom portion, thereby only the copper diffusion preventing film portion to be removed can be removed. The method can extend a durable length of time of a wire and can reduce a resistance of the metal wires in a connecting hole bottom portion by removing a copper diffusion preventing film on the bottom portion of the connecting hole.Type: GrantFiled: March 25, 1997Date of Patent: October 12, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Masahiro Inohara, Minakshisundaran Balasubramanian Anand, Tadashi Matsuno