Abstract: In some examples, separate main I/O (MIO) lines may be used for writing to different banks of a memory array. In some examples, separate MIO lines may be used for writing to and reading from different memory banks. In some examples, the MIO lines for some banks may be used as shield lines between the MIO lines for other banks.

Abstract: Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.

Abstract: Disclosed herein is an apparatus that includes first register circuits configured to store a first address, and a comparing circuit configured to compare the first address with a second address. The comparing circuit includes first and second circuit sections. In a first operation mode, the comparing circuit is configured to activate a match signal when the first circuit section detects that the first bit group of the first address matches with the third bit group of the second address and the second circuit section detects that the second bit group of the first address matches with the fourth bit group of the second address. In a second operation mode, the comparing circuit is configured to activate the match signal when the first circuit section detects that the first bit group matches with the third bit group regardless of the second and fourth bit groups.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.

Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes during a refresh operation, determining a respective row of a memory cells slated for refresh in each of a plurality of sections of a memory bank of a memory device, and determining whether the respective row of memory cells slated for refresh for a particular section of the plurality of sections of the memory bank has been repaired. The example method further includes in response to a determination that the row of memory cells slated for refresh has been repaired, cause a refresh within the particular section of the memory bank to be skipped while contemporaneously performing a refresh of the rows of memory cells slated for refresh in other sections of the plurality of sections of the memory bank to be refreshed.

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes during a refresh operation, determining a respective row of a memory cells slated for refresh in each of a plurality of sections of a memory bank of a memory device, and determining whether the respective row of memory cells slated for refresh for a particular section of the plurality of sections of the memory bank has been repaired. The example method further includes in response to a determination that the row of memory cells slated for refresh has been repaired, cause a refresh within the particular section of the memory bank to be skipped while contemporaneously performing a refresh of the rows of memory cells slated for refresh in other sections of the plurality of sections of the memory bank to be refreshed.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes during a refresh operation, determining a respective row of a memory cells slated for refresh in each of a plurality of sections of a memory bank of a memory device, and determining whether the respective row of memory cells slated for refresh for a particular section of the plurality of sections of the memory bank has been repaired. The example method further includes in response to a determination that the row of memory cells slated for refresh has been repaired, cause a refresh within the particular section of the memory bank to be skipped while contemporaneously performing a refresh of the rows of memory cells slated for refresh in other sections of the plurality of sections of the memory bank to be refreshed.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.

Abstract: In some examples, separate main I/O (MIO) lines may be used for writing to different banks of a memory array. In some examples, separate MIO lines may be used for writing to and reading from different memory banks. In some examples, the MIO lines for some banks may be used as shield lines between the MIO lines for other banks.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.

Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.

Abstract: Apparatuses, systems, and methods for data strobe write timing. A memory device may receive a data strobe clock signal and serial write data during a write operation. A deserializer circuit of the memory may convert the serial write data into parallel write data using timing based on the data strobe clock signal. For example, one or more internal signals may be generated based on the data strobe clock signal and used to activate various operations of the deserializer circuit. The data strobe clock signal may also be used to activate bit lines of the memory device in order to write the parallel write data to memory cells along those activated bit lines. The memory may also receive a system clock, separate from the data strobe clock signal, which may be used for other operations of the memory. For example, in a read operation, the bit lines may be activated with timing based on the system clock.