Patents by Inventor Minari Arai

Minari Arai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11373725
    Abstract: Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: June 28, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Zer Liang, Minari Arai, Takuya Nakanishi
  • Publication number: 20220199141
    Abstract: Apparatuses and methods for refreshing memory of a semiconductor device are described. An example method includes during a refresh operation, determining a respective row of a memory cells slated for refresh in each of a plurality of sections of a memory bank of a memory device, and determining whether the respective row of memory cells slated for refresh for a particular section of the plurality of sections of the memory bank has been repaired. The example method further includes in response to a determination that the row of memory cells slated for refresh has been repaired, cause a refresh within the particular section of the memory bank to be skipped while contemporaneously performing a refresh of the rows of memory cells slated for refresh in other sections of the plurality of sections of the memory bank to be refreshed.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 23, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Minari Arai
  • Patent number: 11340984
    Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Takuya Nakanishi, Toru Ishikawa, Minari Arai
  • Publication number: 20220066875
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Application
    Filed: October 13, 2021
    Publication date: March 3, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toru Ishikawa, Minari Arai
  • Publication number: 20220020422
    Abstract: Disclosed herein is an apparatus that includes first and second digit lines, a sense amplifier configured to amplify a potential difference between the first and second digit lines, a driver circuit configured to drive each of the first and second digit lines to different one of first and second logic levels from each other, a first transistor coupled between the driver circuit and the first digit line, a second transistor coupled between the driver circuit and the second digit line, and a control circuit configured to supply a first potential to control electrodes of the first and second transistors in response to a write command, and supply a second potential different from the first potential to the control electrodes of the first and second transistors in response to a read command.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 20, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Katsuhiro Kitagawa, Toru Ishikawa, Minari Arai, Nobuki Takahashi
  • Publication number: 20220005522
    Abstract: In some examples, separate main I/O (MIO) lines may be used for writing to different banks of a memory array. In some examples, separate MIO lines may be used for writing to and reading from different memory banks. In some examples, the MIO lines for some banks may be used as shield lines between the MIO lines for other banks.
    Type: Application
    Filed: July 2, 2020
    Publication date: January 6, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: YUHEI TAKAHASHI, MINARI ARAI
  • Publication number: 20210407611
    Abstract: Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.
    Type: Application
    Filed: June 25, 2020
    Publication date: December 30, 2021
    Inventors: Zer Liang, Minari Arai, Takuya Nakanishi
  • Publication number: 20210406123
    Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Takuya Nakanishi, Toru Ishikawa, Minari Arai
  • Patent number: 11169876
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Minari Arai
  • Patent number: 11164623
    Abstract: Apparatuses, systems, and methods for data strobe write timing. A memory device may receive a data strobe clock signal and serial write data during a write operation. A deserializer circuit of the memory may convert the serial write data into parallel write data using timing based on the data strobe clock signal. For example, one or more internal signals may be generated based on the data strobe clock signal and used to activate various operations of the deserializer circuit. The data strobe clock signal may also be used to activate bit lines of the memory device in order to write the parallel write data to memory cells along those activated bit lines. The memory may also receive a system clock, separate from the data strobe clock signal, which may be used for other operations of the memory. For example, in a read operation, the bit lines may be activated with timing based on the system clock.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: November 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kohei Nakamura, Minari Arai
  • Publication number: 20210202004
    Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.
    Type: Application
    Filed: February 25, 2021
    Publication date: July 1, 2021
    Inventors: Toru Ishikawa, Minari Arai
  • Publication number: 20210200630
    Abstract: Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. One or more error correction code (ECC) may be used to determine if the bits of information contain any errors. To mitigate the effects of failures of adjacent memory cells, the information may be divided into a first group and a second group, where each group contains information from memory cells which are non-adjacent to other memory cells of that group. Each group of information may include data bits and parity bits used to correct those data bits. For example, as part of a read operation, a first ECC circuit may receive information from even numbered memory cells, while a second ECC circuit may receive information from odd numbered memory cells.
    Type: Application
    Filed: January 21, 2020
    Publication date: July 1, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toru Ishikawa, Minari Arai
  • Patent number: 10984868
    Abstract: Methods of operating a memory device are disclosed. A method may include enabling a first and second row section units a number of row section units of a memory device in response to a row address. The method may also include comparing a selected column address to a number of column addresses of defective memory cells of a first row section of the first row section unit. Moreover, in response to the selected column address matching a first column address of the number of column addresses, the method may include activating a second row section of the second row section unit, conveying a redundant column select signal to the memory array to select a redundant memory cell of the second row section. Memory devices and systems are also disclosed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Toru Ishikawa, Minari Arai
  • Publication number: 20100156500
    Abstract: Disclosed is a semiconductor device having an output circuit that may be used to advantage in case the semiconductor device may possibly be used under different power supply voltages. The semiconductor device includes a signal terminal having at least the function of an output terminal, a power supply terminal, and an output circuit having first and second output buffer circuits. The first and second output buffer circuits are supplied with a supply power voltage from the power supply terminal and receive an inner output signal to drive the signal terminal. The semiconductor device also includes a power supply voltage discrimination circuit that discriminates the potential level of the power supply voltage to control the operation of the output circuit based on the result of discrimination. A first output buffer circuit is activated and a second output buffer circuit is deactivated in case the power supply voltage discrimination circuit has decided that the power supply voltage is at a first potential.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 24, 2010
    Applicant: Elpida Memory, Inc.
    Inventors: Yasushi Matsubara, Minari Arai
  • Patent number: 7710792
    Abstract: Disclosed is a semiconductor device comprising: a signal selecting circuit for receiving, at first and second inputs thereof, respectively, a first signal output from a first initial-stage circuit that receives a data strobe signal from a first terminal, which is an input/output terminal, and a second signal output from a second initial-stage circuit that receives a data mask signal from a second terminal, which is an input terminal, and based upon a control signal that is supplied thereto, outputting the first and second signals from first and second outputs or interchanging the first and second signals and outputting the interchanged first and second signals from the second and first outputs; a buffer circuit for receiving an output signal from a third initial-stage circuit that receives a data signal from a data terminal; and a data latch circuit for latching a signal from the buffer circuit.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: May 4, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Minari Arai
  • Patent number: 7623398
    Abstract: Disclosed is a module where semiconductor memory devices each having a DLL (Delay Lock Loop) are stacked or a multi-chip module (MCM) having the semiconductor memory devices, a dedicated pad for sharing a clock signal between one of the semiconductor memory devices and other semiconductor memory device is included. The clock signal is delay adjusted by the DLL. The DLL in the one semiconductor memory device is operated, while the DLL in the other semiconductor memory device is not operated. A flying lock clock signal synchronized with an external differential clock signal and generated from a clock signal delay adjusted by the DLL is output from the dedicated pad of the one semiconductor memory device. The other semiconductor memory device receives the flying lock clock signal from the dedicated pad.
    Type: Grant
    Filed: September 4, 2007
    Date of Patent: November 24, 2009
    Assignee: Elpida Memory, Inc
    Inventor: Minari Arai
  • Patent number: 7548099
    Abstract: In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value when the first signal and the delayed first signal meet a predetermined condition. A delay section has a second delay value and generates an output signal based on a summation of the fixed adjustment value and the second delay value, and a set multiplication value in response to a trigger signal such that the output signal in an active state for a period corresponding to the set multiplication value.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: June 16, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Minari Arai
  • Publication number: 20080298138
    Abstract: Disclosed is a semiconductor device comprising: a signal selecting circuit for receiving, at first and second inputs thereof, respectively, a first signal output from a first initial-stage circuit that receives a data strobe signal from a first terminal, which is an input/output terminal, and a second signal output from a second initial-stage circuit that receives a data mask signal from a second terminal, which is an input terminal, and based upon a control signal that is supplied thereto, outputting the first and second signals from first and second outputs or interchanging the first and second signals and outputting the interchanged first and second signals from the second and first outputs; a buffer circuit for receiving an output signal from a third initial-stage circuit that receives a data signal from a data terminal; and a data latch circuit for latching a signal from the buffer circuit.
    Type: Application
    Filed: May 30, 2008
    Publication date: December 4, 2008
    Inventor: Minari Arai
  • Publication number: 20080054965
    Abstract: Disclosed is a module where semiconductor memory devices each having a DLL (Delay Lock Loop) are stacked or a multi-chip module (MCM) having the semiconductor memory devices, a dedicated pad for sharing a clock signal between one of the semiconductor memory devices and other semiconductor memory device is included. The clock signal is delay adjusted by the DLL. The DLL in the one semiconductor memory device is operated, while the DLL in the other semiconductor memory device is not operated. A flying lock clock signal synchronized with an external differential clock signal and generated from a clock signal delay adjusted by the DLL is output from the dedicated pad of the one semiconductor memory device. The other semiconductor memory device receives the flying lock clock signal from the dedicated pad.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 6, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Minari ARAI
  • Publication number: 20070291559
    Abstract: In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value when the first signal and the delayed first signal meet a predetermined condition. A delay section has a second delay value and generates an output signal based on a summation of the fixed adjustment value and the second delay value, and a set multiplication value in response to a trigger signal such that the output signal in an active state for a period corresponding to the set multiplication value.
    Type: Application
    Filed: August 3, 2007
    Publication date: December 20, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Minari Arai