Abstract: A semiconductor memory device includes a plurality of sense amplifiers which are divided into two groups. There are provided drive wires each extending to an associated one of the sense amplifier groups and being used to independently drive the associated group. The length of each drive wire being thereby reduced up to a half, to operated at a high speed.

Abstract: The output circuit according to this invention includes a first transistor (output transistor) provided between a first power terminal and an output terminal and receiving a first input signal into its gate via a voltage boosting circuit, a second transistor provided between a second power terminal and the output terminal and receiving a second input signal into its gate, a third and a fourth transistors connected in series between the gate of the first transistor and the output terminal with their respective gates connected to the second power terminal, and a fifth transistor provided between the first power terminal and the node of the third and fourth transistors with its gate connected to the gate of the output transistor.