Patents by Inventor Minchan GWAK

Minchan GWAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220399449
    Abstract: A semiconductor device includes an active region on a substrate, gate structures intersecting the active region on the substrate, source/drain regions on both sides of the gate structures, a contact structure in a contact hole exposing the source/drain regions, the contact structure comprising a barrier layer and a plug layer, and an insulating pattern in a remaining space of the contact hole, wherein the contact structure includes a first portion filling a lower portion of the contact hole and a second portion protruding from a region of the first portion, the plug layer extends continuously from the first portion to the second portion, and the barrier layer of the second portion has upper ends at a level lower than an upper surface of the plug layer of the second portion on both sides of the plug layer of the second portion.
    Type: Application
    Filed: February 24, 2022
    Publication date: December 15, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Doohyun LEE, Heonjong SHIN, Minchan GWAK
  • Publication number: 20220384591
    Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.
    Type: Application
    Filed: December 9, 2021
    Publication date: December 1, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Doohyun LEE, Heonjong SHIN, Seon-Bae KIM, Minchan GWAK, Jinyoung PARK, Hyunho PARK
  • Publication number: 20220216107
    Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
  • Publication number: 20220149043
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Application
    Filed: January 24, 2022
    Publication date: May 12, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heonjong SHIN, Sunghun JUNG, Minchan GWAK, Yongsik JEONG, Sangwon JEE, Sora YOU, Doohyun LEE
  • Patent number: 11309218
    Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
  • Patent number: 11264386
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: March 1, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: HeonJong Shin, Sunghun Jung, Minchan Gwak, Yongsik Jeong, Sangwon Jee, Sora You, Doohyun Lee
  • Publication number: 20220020860
    Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Inventors: DOOHYUN LEE, HEONJONG SHIN, MINCHAN GWAK, HYUNHO PARK, SUNGHUN JUNG, YONGSIK JEONG, SANGWON JEE, INCHAN HWANG
  • Patent number: 11177362
    Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: November 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doohyun Lee, Heonjong Shin, Minchan Gwak, Hyunho Park, Sunghun Jung, Yongsik Jeong, Sangwon Jee, Inchan Hwang
  • Publication number: 20210082757
    Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.
    Type: Application
    Filed: June 11, 2020
    Publication date: March 18, 2021
    Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
  • Publication number: 20210057536
    Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.
    Type: Application
    Filed: March 25, 2020
    Publication date: February 25, 2021
    Inventors: DOOHYUN LEE, HEONJONG SHIN, MINCHAN GWAK, HYUNHO PARK, SUNGHUN JUNG, YONGSIK JEONG, SANGWON JEE, INCHAN HWANG
  • Patent number: 10923475
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heonjong Shin, Sunghun Jung, Minchan Gwak, Yongsik Jeong, Sangwon Jee, Sora You, Doohyun Lee
  • Publication number: 20210013206
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Application
    Filed: September 30, 2020
    Publication date: January 14, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: HeonJong SHIN, Sunghun JUNG, Minchan GWAK, Yongsik JEONG, Sangwon JEE, Sora YOU, Doohyun LEE
  • Patent number: 10861860
    Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
  • Publication number: 20200075595
    Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.
    Type: Application
    Filed: April 23, 2019
    Publication date: March 5, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heonjong SHIN, Sunghun JUNG, Minchan GWAK, Yongsik JEONG, Sangwon JEE, Sora YOU, Doohyun LEE
  • Publication number: 20190244965
    Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
    Type: Application
    Filed: April 17, 2019
    Publication date: August 8, 2019
    Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
  • Patent number: 10332898
    Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 25, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
  • Publication number: 20180145082
    Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.
    Type: Application
    Filed: June 28, 2017
    Publication date: May 24, 2018
    Inventors: Seungsoo HONG, JeongYun LEE, GeumJung SEONG, HyunHo JUNG, Minchan GWAK, Kyungseok MIN, Youngmook OH, Jae-Hoon WOO, Bora LIM