Patents by Inventor Minchan GWAK
Minchan GWAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220399449Abstract: A semiconductor device includes an active region on a substrate, gate structures intersecting the active region on the substrate, source/drain regions on both sides of the gate structures, a contact structure in a contact hole exposing the source/drain regions, the contact structure comprising a barrier layer and a plug layer, and an insulating pattern in a remaining space of the contact hole, wherein the contact structure includes a first portion filling a lower portion of the contact hole and a second portion protruding from a region of the first portion, the plug layer extends continuously from the first portion to the second portion, and the barrier layer of the second portion has upper ends at a level lower than an upper surface of the plug layer of the second portion on both sides of the plug layer of the second portion.Type: ApplicationFiled: February 24, 2022Publication date: December 15, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Doohyun LEE, Heonjong SHIN, Minchan GWAK
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Publication number: 20220384591Abstract: A semiconductor device may include an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern connected to the source/drain pattern, a gate electrode on the channel pattern, an active contact on the source/drain pattern, a first lower interconnection line on the gate electrode, and a second lower interconnection line on the active contact and at the same level as the first lower interconnection line. The gate electrode may include an electrode body portion and an electrode protruding portion, wherein the electrode protruding portion protrudes from a top surface of the electrode body portion and is in contact with the first lower interconnection line thereon. The active contact may include a contact body portion and a contact protruding portion, wherein the contact protruding portion protrudes from a top surface of the contact body portion and is in contact with the second lower interconnection line thereon.Type: ApplicationFiled: December 9, 2021Publication date: December 1, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Doohyun LEE, Heonjong SHIN, Seon-Bae KIM, Minchan GWAK, Jinyoung PARK, Hyunho PARK
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Publication number: 20220216107Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
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Publication number: 20220149043Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Heonjong SHIN, Sunghun JUNG, Minchan GWAK, Yongsik JEONG, Sangwon JEE, Sora YOU, Doohyun LEE
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Patent number: 11309218Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.Type: GrantFiled: June 11, 2020Date of Patent: April 19, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
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Patent number: 11264386Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.Type: GrantFiled: September 30, 2020Date of Patent: March 1, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: HeonJong Shin, Sunghun Jung, Minchan Gwak, Yongsik Jeong, Sangwon Jee, Sora You, Doohyun Lee
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Publication number: 20220020860Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Inventors: DOOHYUN LEE, HEONJONG SHIN, MINCHAN GWAK, HYUNHO PARK, SUNGHUN JUNG, YONGSIK JEONG, SANGWON JEE, INCHAN HWANG
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Patent number: 11177362Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.Type: GrantFiled: March 25, 2020Date of Patent: November 16, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Doohyun Lee, Heonjong Shin, Minchan Gwak, Hyunho Park, Sunghun Jung, Yongsik Jeong, Sangwon Jee, Inchan Hwang
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Publication number: 20210082757Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.Type: ApplicationFiled: June 11, 2020Publication date: March 18, 2021Inventors: Sungmoon Lee, Minchan Gwak, Heonjong Shin, Yongsik Jeong, Yeongchang Roh, Doohyun Lee, Sunghun Jung, Sangwon Jee
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Publication number: 20210057536Abstract: A semiconductor device including: a substrate that includes a first active region and a second active region; a first source/drain pattern on the first active region; a second source/drain pattern on the second active region; a separation dielectric pattern on the substrate between the first source/drain pattern and the second source/drain pattern; and a first contact pattern on the first source/drain pattern, wherein the first contact pattern includes: a first metal pattern; a first barrier pattern between the first metal pattern and the first source/drain pattern; and a second barrier pattern between the first barrier pattern and the first source/drain pattern, wherein the first barrier pattern contacts the separation dielectric pattern and extends along a sidewall of the first metal pattern adjacent to the separation dielectric pattern.Type: ApplicationFiled: March 25, 2020Publication date: February 25, 2021Inventors: DOOHYUN LEE, HEONJONG SHIN, MINCHAN GWAK, HYUNHO PARK, SUNGHUN JUNG, YONGSIK JEONG, SANGWON JEE, INCHAN HWANG
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Patent number: 10923475Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.Type: GrantFiled: April 23, 2019Date of Patent: February 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Heonjong Shin, Sunghun Jung, Minchan Gwak, Yongsik Jeong, Sangwon Jee, Sora You, Doohyun Lee
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Publication number: 20210013206Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: HeonJong SHIN, Sunghun JUNG, Minchan GWAK, Yongsik JEONG, Sangwon JEE, Sora YOU, Doohyun LEE
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Patent number: 10861860Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.Type: GrantFiled: April 17, 2019Date of Patent: December 8, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
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Publication number: 20200075595Abstract: A semiconductor device may include a substrate including an active pattern extending in a first direction, a gate electrode running across the active pattern and extending in a second direction intersecting the first direction, a source/drain pattern on the active pattern and adjacent to a side of the gate electrode, an active contact in a contact hole exposing the source/drain pattern, an insulating pattern filling a remaining space of the contact hole in which the active contact is provided, a first via on the active contact, and a second via on the gate electrode. The active contact may include a first segment that fills a lower portion of the contact hole and a second segment that vertically protrudes from the first segment. The first via is connected to the second segment. The insulating pattern is adjacent in the first direction to the second via.Type: ApplicationFiled: April 23, 2019Publication date: March 5, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Heonjong SHIN, Sunghun JUNG, Minchan GWAK, Yongsik JEONG, Sangwon JEE, Sora YOU, Doohyun LEE
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Publication number: 20190244965Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.Type: ApplicationFiled: April 17, 2019Publication date: August 8, 2019Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
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Patent number: 10332898Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.Type: GrantFiled: June 28, 2017Date of Patent: June 25, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seungsoo Hong, JeongYun Lee, GeumJung Seong, HyunHo Jung, Minchan Gwak, Kyungseok Min, Youngmook Oh, Jae-Hoon Woo, Bora Lim
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Publication number: 20180145082Abstract: A semiconductor device includes a first active pattern and a second active pattern on a substrate, a first gate electrode and a second gate electrode respectively across the first active pattern and the second active pattern, a first insulation pattern between and separating the first and second gate electrodes, a gate spacer on a sidewall of the first gate electrode, on a sidewall of the second gate electrode, and on a sidewall of the first insulation pattern, and a second insulation pattern between the gate spacer and the sidewall of the first insulation pattern, wherein the first gate electrode, the first insulation pattern, and the second gate electrode are arranged along a first direction, and wherein the gate spacer extends in the first direction.Type: ApplicationFiled: June 28, 2017Publication date: May 24, 2018Inventors: Seungsoo HONG, JeongYun LEE, GeumJung SEONG, HyunHo JUNG, Minchan GWAK, Kyungseok MIN, Youngmook OH, Jae-Hoon WOO, Bora LIM