Patents by Inventor Minchan LEE

Minchan LEE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145556
    Abstract: An embodiment of the present inventive step provides a semiconductor device, comprising: first and second fin-type active patterns disposed on an upper surface of a substrate, and having different widths; first and second gate structures crossing the first and second fin-type active patterns, respectively; first and second source/drain regions disposed on the first and second fin-type active patterns, respectively; first and second contact structures connected to the first and second source/drain regions, respectively; a gate isolation structure adjacent to the first fin-type active pattern having a relatively large width; a buried conductive structure contacting one end surface of the gate isolation structure, and connected to the second contact structure; a conductive through-structure extending from a lower surface of the substrate, and connected to the buried conductive structure; and a first wiring layer electrically connected to the first contact structure and the buried conductive structure.
    Type: Application
    Filed: October 23, 2023
    Publication date: May 2, 2024
    Inventors: Gukhee Kim, Kyoungwoo Lee, Sangcheol Na, Minchan Gwak, Youngwoo Kim, Hojun Kim, Dongick Lee
  • Publication number: 20240128161
    Abstract: Provided is an integrated circuit device including a substrate, a plurality of semiconductor patterns on a first surface of the substrate, a gate electrode extending in a first direction and surrounding the semiconductor patterns, a source/drain region disposed on one side of the gate electrode, a vertical power wiring layer extending in a second direction, a liner structure including a first liner and a second liner, the first liner disposed on a lower portion of a sidewall of the vertical power wiring layer and including a first insulating material, and the second liner disposed on an upper portion of the sidewall of the vertical power wiring layer and including a second insulating material, a first contact disposed on the source/drain region and the vertical power wiring layer, and a back wiring structure disposed on a second surface of the substrate and electrically connected to the vertical power wiring layer.
    Type: Application
    Filed: October 11, 2023
    Publication date: April 18, 2024
    Inventors: Sungmoon Lee, Sangcheol Na, Sora You, Kyoungwoo Lee, Minchan Gwak, Youngwoo Kim, Jinkyu Kim, Seungmin Cha
  • Publication number: 20240072117
    Abstract: A semiconductor device includes a substrate having a first and second active patterns therein, first and second source/drain patterns extending on the first and second active patterns, respectively, and an active contact on the first and second source/drain patterns. An upper contact is provided, which extends from the active contact towards the substrate, and between the first and second active patterns. A lower power interconnection line is provided, which is buried in a lower portion of the substrate and includes: a buried interconnection portion having a line shape, and a lower contact portion extending vertically from the buried interconnection portion to a bottom surface of the upper contact. A barrier pattern is provided, which extends between the lower contact portion and the upper contact, but not between the buried interconnection portion and the lower contact portion.
    Type: Application
    Filed: April 26, 2023
    Publication date: February 29, 2024
    Inventors: Gukhee Kim, Kyoungwoo Lee, Jeewoong Kim, Sangcheol Na, Minchan Gwak, Youngwoo Kim, Anthony Dongick Lee
  • Patent number: 11133917
    Abstract: An apparatus and a method for sampling a signal in a wireless communication system that employs a time division duplex (TDD) scheme are provided. According to various embodiments of the present disclosure, a method for a base station being operated in a wireless communication system that employs TDD comprises the steps of: determining a switching section for controlling a conversion mode of a sampling rate conversion circuit based on a timing advance (TA) value with respect to a signal transmitted by a terminal; generating a switching signal within the switching section; changing the conversion mode from a first mode to second mode in response to the switching signal; and changing a sampling rate of a transmission signal or reception signal based on the second mode.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 28, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minchan Lee, Hyeongrae Son
  • Patent number: 11081075
    Abstract: The present inventive concept is related to a display device in which a compensated voltage is applied to a gate line by compensating for a voltage drop of a voltage applied to the gate line.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: August 3, 2021
    Inventors: Hyunwook Lee, Pilgyu Kang, Minchan Lee, Sungjin Lee, Chanyoung Lim, Solip Jeong
  • Publication number: 20200162231
    Abstract: An apparatus and a method for sampling a signal in a wireless communication system that employs a time division duplex (TDD) scheme are provided. According to various embodiments of the present disclosure, a method for a base station being operated in a wireless communication system that employs TDD comprises the steps of: determining a switching section for controlling a conversion mode of a sampling rate conversion circuit based on a timing advance (TA) value with respect to a signal transmitted by a terminal; generating a switching signal within the switching section; changing the conversion mode from a first mode to second mode in response to the switching signal; and changing a sampling rate of a transmission signal or reception signal based on the second mode.
    Type: Application
    Filed: July 4, 2018
    Publication date: May 21, 2020
    Inventors: Minchan LEE, Hyeongrae SON
  • Publication number: 20190287475
    Abstract: The present inventive concept is related to a display device in which a compensated voltage is applied to a gate line by compensating for a voltage drop of a voltage applied to the gate line.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 19, 2019
    Inventors: Hyunwook LEE, Pilgyu KANG, Minchan LEE, Sungjin LEE, Chanyoung LIM, Solip JEONG