Abstract: A display device includes a first substrate, a second substrate disposed on the first substrate, an image display layer disposed between the first substrate and the second substrate, a gate driver disposed at a first side surface of the first substrate, a data driver disposed at a second side surface of the first substrate, and conductive layers respectively disposed in recesses recessed from the first side surface of the first substrate. The gate driver is electrically connected to the conductive layers.

Abstract: A display device includes a first substrate, a second substrate disposed on the first substrate, an image display layer disposed between the first substrate and the second substrate, a gate driver disposed at a first side surface of the first substrate, a data driver disposed at a second side surface of the first substrate, and conductive layers respectively disposed in recesses recessed from the first side surface of the first substrate. The gate driver is electrically connected to the conductive layers.

Abstract: A gate driving circuit includes a pull-up control part applying a previous carry signal of one of previous stages to a first node in response to the previous carry signal, a pull-up part outputting a clock signal as an N-th gate output signal in response to a signal at the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal at the first node, a first pull-down part pulling down the signal at the first node to a second off voltage in response to a first next carry signal of one of next stages and a second pull-down part pulling down the N-th gate output signal to a first off voltage in response to a second next carry signal of one of the next stages different from the first next carry signal.

Abstract: A gate driving circuit includes a pull-up control part applying a previous carry signal of one of previous stages to a first node in response to the previous carry signal, a pull-up part outputting a clock signal as an N-th gate output signal in response to a signal at the first node, a carry part outputting the clock signal as an N-th carry signal in response to the signal at the first node, a first pull-down part pulling down the signal at the first node to a second off voltage in response to a first next carry signal of one of next stages and a second pull-down part pulling down the N-th gate output signal to a first off voltage in response to a second next carry signal of one of the next stages different from the first next carry signal.