Patents by Inventor Mincheol KWAK

Mincheol KWAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240152064
    Abstract: A photolithography system includes a light source, a photomask stage, a projection optical system and a wafer stage, and the projection optical system includes an anamorphic lens. In a photolithography method, a wafer and a photomask are mounted on the wafer stage and the photomask stage, respectively, and a first exposure process is performed using the photomask to transfer layouts of patterns included in the photomask to a first half field of the wafer. A relative position of the photomask with respect to the wafer is changed, and a second exposure process is performed to transfer the layouts of the patterns included in the photomask to a second half field of the wafer.
    Type: Application
    Filed: September 25, 2023
    Publication date: May 9, 2024
    Inventors: Mincheol KWAK, Jeongjin LEE, Seungyoon LEE, Chan HWANG
  • Patent number: 11380552
    Abstract: In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.
    Type: Grant
    Filed: April 25, 2020
    Date of Patent: July 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunchul Yoon, Mincheol Kwak, Joonghee Kim, Jihee Kim, Yeongshin Park, Jungheun Hwang
  • Publication number: 20210098260
    Abstract: In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.
    Type: Application
    Filed: April 25, 2020
    Publication date: April 1, 2021
    Inventors: Hyunchul YOON, Mincheol KWAK, Joonghee KIM, Jihee KIM, Yeongshin PARK, Jungheun HWANG