Abstract: A semiconductor device includes: an active region on a substrate; a gate structure intersecting the active region and including a gate electrode; a source/drain region on the active region; a first contact structure on and connected to the source/drain region; first and second insulating layers on the gate and first contact structures; a second contact structure connected to the gate electrode and including: a first contact via in the first insulating layer; and a first conductive cap layer in the second insulating layer and on the first contact via; a via structure connected to the first contact structure, the via structure including: a second contact via in the first insulating layer; and a second conductive cap layer in the second insulating layer and on the second contact via; and interconnection lines on the second insulating layer connected to the second contact structure and the via structure.

Abstract: A pretreatment system and method is used for testing a metal component. The pretreatment system includes a robot, a plurality of arms having relative rotation with respect to each other, and a foremost arm movable within an operating radius. A gripper device mounted at the foremost arm includes a first gripper unit and a second gripper unit. A sample input device includes a sample input unit lifting device that includes a dosing head mounted thereon movable. A tube holder cup is disposed below the sample input lifting device and configured to input the sample into the tube. An acid injection device is configured to inject acid into the tube or inject distilled water into the tube containing the acid in which the sample is dissolved. A vision device acquires an image of a set portion of a tube containing a sample solution in which the sample is dissolved in acid.

Abstract: An integrated circuit device includes a backside insulating structure including an etch stop pattern, gate lines arranged over the backside insulating structure and each overlapping the etch stop pattern in a vertical direction, source/drain regions respectively arranged one-by-one between the gate lines, and a backside via contact passing through the etch stop pattern in the vertical direction and connected to a first source/drain region selected from the source/drain regions, wherein the backside via contact includes a stepped portion, which is apart from a first vertical level in the vertical direction by as much as a first distance and has a change in the width of the backside via contact in a horizontal direction at a second vertical level that is adjacent to the etch stop pattern, the first vertical level being closest to the plurality of gate lines in the backside insulating structure.

Abstract: Provided is a gene delivery composition including nitrogen-doped graphene quantum dots as an active ingredient, the nitrogen-doped graphene quantum dots of the present invention exhibiting excellent safety and low cytotoxicity in room temperature, and having positively charged surfaces, thereby binding with negatively charged genes through electrostatic attractive force and thus being capable of delivering the genes into cells, and exhibiting excellent gene delivery efficiency and transfection efficiency, thereby being expected to be usefully employable for a gene delivery platform for gene therapy.

Abstract: A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.