Abstract: A method for fabricating a semiconductor device includes forming a cell mold including a dummy channel pattern and a plurality of mold layers over a lower structure; forming a horizontal conductive line that intersects with the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element that is coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line that is coupled to a second side of the channel layer.

Abstract: A method for fabricating a semiconductor device includes: forming an isolation layer that defines a plurality of active regions over a substrate; forming a bit line stack over the substrate; forming a main hard mask layer over the bit line stack; forming a plurality of first sacrificial mask layers over the main hard mask layer; forming a plurality of second sacrificial mask layers overlapping with both side ends of the first sacrificial mask layers over the first sacrificial mask layers; forming a main hard mask layer pattern by using the first and second sacrificial mask layers as barriers and etching the main hard mask layer; and forming a bit line structure by using the main hard mask layer pattern as a barrier and etching the bit line stack.

Abstract: A semiconductor device includes a bit line; a plurality of first semiconductor pillars disposed over the bit line; a plurality of first cell contact plugs disposed between the first semiconductor pillars; a plurality of second semiconductor pillars coupled to the first cell contact plugs; a plurality of second cell contact plugs disposed between the second semiconductor pillars and coupled to the first semiconductor pillars; and a plurality of capacitors respectively coupled to the second semiconductor pillars and the second cell contact plugs.

Abstract: A semiconductor device includes: a substrate; a bit line positioned over the substrate and extending in a first direction; a first dielectric layer covering the bit line; a first channel layer positioned over the first dielectric layer; at least one word line positioned over the first channel layer and extending in a second direction crossing the first direction; a second dielectric layer at least filling a space between adjacent word lines; a first contact coupled to the bit line by penetrating the second dielectric layer, the first channel layer, and the first dielectric layer; a third dielectric layer positioned over the word line, the second dielectric layer, and the first contact; and a second contact coupled to the first channel layer by penetrating the third dielectric layer and the second dielectric layer.

Abstract: A method for fabricating a semiconductor device includes: forming a first oxide layer containing a first element over a first electrode layer; forming a second oxide layer containing a second element over the first oxide layer; forming a stacked structure in which a plurality of first oxide layers and a plurality of second oxide layers are alternately stacked by repeating the forming of the first oxide layer and the forming of the second oxide layer a plurality of times; and forming a second electrode layer over the stacked structure, wherein a thickness of a lowermost first oxide layer among the plurality of first oxide layers is greater than a thickness of each of other first oxide layers.

Abstract: A memory device includes a memory cell array including a plurality of memory cells; a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including: a first operational circuit configured to perform a first operation according to a first sensing control signal; and a second operational circuit configured to perform a second operation according to a second sensing control signal; and an operational monitoring circuit configured to provide the first sensing control signal or the second sensing control signal by monitoring whether at least some of the memory cells have a ferroelectric property.

Abstract: A semiconductor device includes: a first common plate extending vertically in a first direction; a second common plate which is spaced apart from the first common plate in a second direction and extends vertically in the first direction; a slit formed between the first common plate and the second common plate; a first memory cell array sharing the first common plate and including first capacitors that are vertically stacked in the first direction; and a second memory cell array sharing the second common plate and including second capacitors that are vertically stacked in the first direction.

Abstract: A semiconductor device includes a plurality of bit line structures formed to be spaced apart from each other over a semiconductor substrate, a first spacer formed on both sidewalls of each of the bit line structures, a lower plug formed between the bit line structures and in contact with the semiconductor substrate, an upper plug positioned over the lower plug and having a greater line width than the lower plug, a middle plug positioned between the lower plug and the upper plug and having a smaller line width than a line width of the lower plug, and a second spacer positioned between the middle plug and the first spacer, wherein the second spacer is thicker than the first spacer.

Abstract: According to various example embodiments, an electronic device is disclosed. The electronic device includes a housing having a first surface facing a first direction and a second surface facing a second, opposing direction. A first area of the first surface includes a plurality of selectable input keys. A second area of the first surface excludes the plurality of keys. A sensor module, such as a fingerprint sensor, is installed to the first area.

Abstract: According to various example embodiments, an electronic device is disclosed. The electronic device includes a housing having a first surface facing a first direction and a second surface facing a second, opposing direction. A first area of the first surface includes a plurality of selectable input keys. A second area of the first surface excludes the plurality of keys. A sensor module, such as a fingerprint sensor, is installed to the first area.

Abstract: A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap.

Abstract: An e-fuse including a substrate including a first active region and a second active region which are spaced from each other by an isolation region, a first program gate and a second program gate which are disposed over the first active region in parallel with each other, a single select gate disposed over the second active region; a sharing doping region formed in the first active region between the first program gate and the second program gate, a first doping region and a second doping region that are formed in the second active region on both sides of the select gate, a first metal line suitable for electrically coupling the sharing doping region to the first doping region and a second metal line connected to the second doping region.

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.

Abstract: A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.

Abstract: A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap.

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.

Abstract: A semiconductor device has a semiconductor substrate including a cell region and a peripheral region and includes: a Silicon-Metal-Silicon (SMS)-structured wafer formed in the cell region, which includes a stacked structure of a first silicon substrate, a metal layer, and a second silicon substrate; and a Silicon On Insulator (SOI)-structured wafer formed in the peripheral region, which includes a stacked structure of the first silicon substrate, a silicon insulation film, and the second silicon substrate.

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.

Abstract: A method for fabricating a semiconductor device includes forming a conductive layer over first and second regions of a semiconductor substrate, forming a trench extended in the first region of the semiconductor substrate through the conductive layer, forming a recessed gate electrode in the trench, doping the conductive layer and the recessed first gate electrode, and forming a second gate electrode by etching the doped conductive layer.

Abstract: An anti-fuse array of a semiconductor device and a method for forming the same are disclosed. The anti-fuse array for a semiconductor device includes a first-type semiconductor substrate formed to define an active region by a device isolation region, a second-type impurity implantation region formed in the active region, a first-type channel region isolated from the semiconductor substrate by the second-type impurity implantation region, a gate electrode formed over the channel region, and a first metal contact formed over the second-type impurity implantation region.