Abstract: The present disclosure includes apparatus, systems, digital logic circuitry and techniques relating to data encoding. A method performed by a system on a chip (SOC) includes receiving data to be output to a memory unit external to the SOC. Also a key for scrambling the received data is received. A proper subset of the key is identified and used to scramble the received data. The scrambled data is output to the memory unit external to the SOC.

Abstract: Cryptographic apparatus having corresponding methods and computer-readable media comprise: a mailbox memory module to store cryptographic commands received from a client over a client bus, wherein the client is external to the cryptographic apparatus; and a secure processor to obtain the cryptographic commands from the mailbox memory module over a first secure internal bus, execute the cryptographic commands, and store a status of execution of the cryptographic commands in the mailbox memory module over the first secure internal bus, wherein the client obtains the status of the cryptographic commands from the mailbox memory module over the client bus.

Abstract: Methods and apparatus for determining approximating polynomials using instruction-embedded coefficients are disclosed. In particular, the methods and apparatus use a plurality of coefficient values stored in a plurality of instructions. The coefficient values are associated with a runtime approximating polynomial of a K-th root family function. The coefficient values and the instructions stored in an instruction memory enable the processor system to determine a K-th root family function approximation value based on the runtime approximating polynomial.

Abstract: An apparatus includes a processor to control a boot-up of an electronic device in response to a detection of tampering with the device. In some embodiments of the invention, the processor may detect tampering by authenticating a source of a boot image used during the boot-up; and the processor may detect tampering by verifying the integrity of the boot image. In some embodiments of the invention, the processor may control a transition of the electronic device from a first state to a second power state in response to a detection of tampering with the device. The electronic device consumes more power in the second power state than in the first power state.

Abstract: A unique processor serial number may be utilized to augment a device key seed stored in a non-volatile memory. In this way, a relatively secure system may be enabled that facilitates renewing the device key. An integrated circuit may include a transport demultiplexer and key logic. The key logic communicates with the processor using a secure protocol. The key logic can generate random numbers that may be hashed with the processor serial number and the device key seed to generate a device key. The device key may be provided to a head end to facilitate secure communications between the head end and the client.

Abstract: Methods and apparatus for determining approximating polynomials using instruction-embedded coefficients are disclosed. In particular, the methods and apparatus use a plurality of coefficient values stored in a plurality of instructions. The coefficient values are associated with a runtime approximating polynomial of a K-th root family function. The coefficient values and the instructions stored in an instruction memory enable the processor system to determine a K-th root family function approximation value based on the runtime approximating polynomial.

Abstract: A multiplication apparatus and system may include a multiplicand buffer to hold a digit of a multiplicand, a multiplier buffer to hold a digit of a multiplier, and a result buffer to hold a carry-free multiplied and accumulated result of the multiplicand and a plurality of reverse ordered digits included in the multiplier. An article, including a machine-accessible medium, may contain data capable of causing a machine to implement a multiplication method, including selecting a multiplicand plurality of digits, reversing the order of a selected multiplier plurality of digits to provide a reversed plurality of digits, and multiplying and accumulating the multiplicand plurality of digits and the reversed plurality of digits to provide a multiplication result.

Abstract: A method and apparatus for protecting information communicated between a first and a second device includes generating a request to a third device, the request including information identifying the first and second devices. The third device verifies the first and second devices based on the information in the request. Predetermined information is sent to at least one of the first and second devices, and the first and second devices authenticate each other based on the predetermined information.

Abstract: A method and apparatus of protecting communications in a receiver having a first and a second module includes issuing a request to a transmitter. The identities of the first and second modules are verified based on information in the request. The transmitter transmits a predetermined message to the receiver after verification. The first and second devices are authenticated based on the predetermined message.

Abstract: A method and apparatus of securely communicating content between a first device and a second device includes sending identification information of the first and second devices to a third device. The third device generates a predetermined message based on the identification information. The first and second devices are authenticated using the predetermined message.

Abstract: An execution unit that performs both Reed-Solomon Error Correction Code (R-S ECC) encoding and R-S ECC syndrome generation within a combinational circuit coupled between an input buffer and an output buffer.

Abstract: An improved method and apparatus for generating syndromes in a Reed-Solomon Error Correction Code decoder is disclosed. An encoder that encodes the modified code polynomial and generates a parity polynomial based on said modified code polynomial, is provided. The encoder provides the parity polynomial to a syndrome generator. The syndrome generator based on the parity polynomial generates syndromes that are provided to an error location unit and an error evaluation unit. The error location unit generates intermediate locations of corrupted symbols in a data block based on the syndromes. The error location unit determines the true location of the corrected symbols in a data block based upon the intermediate values by subtracting each intermediate location from a constant M (where M is the total number of generated parity symbols) and performing a modulo operation on the difference with 2.sup.N (where N is the bit-length of the data symbol in the Galois Field).