Abstract: An electrostatic discharge (ESD) protection circuit with electrical overstress (EOS) and latch-up immunity has a main ESD circuit, a voltage detection circuit and an electrostatic driving circuit. The main ESD circuit is coupled between a first rail and a second rail and has a control end. The main ESD circuit is configured to establish an electrical connection between the first rail and the second rail based on a voltage of the control end. The voltage detection circuit is coupled between the first rail and the second rail for setting the voltage of the control end when a voltage of the first rail is greater than a limiting voltage. The electrostatic driving circuit is used to drive the main ESD circuit when an ESD phenomenon occurs.

Abstract: An electrostatic discharge (ESD) protection circuit with electrical overstress (EOS) and latch-up immunity has a main ESD circuit, a voltage detection circuit and an electrostatic driving circuit. The main ESD circuit is coupled between a first rail and a second rail and has a control end. The main ESD circuit is configured to establish an electrical connection between the first rail and the second rail based on a voltage of the control end. The voltage detection circuit is coupled between the first rail and the second rail for setting the voltage of the control end when a voltage of the first rail is greater than a limiting voltage. The electrostatic driving circuit is used to drive the main ESD circuit when an ESD phenomenon occurs.

Abstract: A method for measuring transconductance of an oscillating circuit is provided. The oscillating circuit includes an inverter. When an input terminal and an output terminal of the inverter are floated, the bias voltage of the inverter is obtained by measuring the output terminal thereof. Based on floating the input terminal and respectively providing a first voltage and a second voltage to the output terminal, a first current corresponding to the first voltage and a second current corresponding to the second voltage are measured from the output terminal. The first voltage and the bias voltage have the same voltage levels. An output resistor value of the inverter is obtained according to the first and second voltages and the first and second currents. The transconductance of the oscillating circuit is obtained according to the output resistor value.

Abstract: An ESD prevention circuit is provided. The ESD prevention circuit comprises a voltage source, a charge-blocking unit, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and an output unit. The charge-blocking unit is coupled to the voltage source and provides a reverse voltage to control the voltage source to remain at a zero potential when an electrostatic voltage is being generated. The first PMOS transistor is coupled to the charge-blocking unit. The first NMOS transistor is coupled to the first PMOS transistor. The second NMOS transistor is coupled to the first PMOS transistor and the first NMOS transistor. The output unit is coupled to the second NMOS transistor. The electrostatic voltage is affected by the charge-blocking unit and does not raise impendence of the turned-on second NMOS transistor.

Abstract: A method for measuring transconductance of an oscillating circuit is provided. The oscillating circuit includes an inverter. When an input terminal and an output terminal of the inverter are floated, the bias voltage of the inverter is obtained by measuring the output terminal thereof. Based on floating the input terminal and respectively providing a first voltage and a second voltage to the output terminal, a first current corresponding to the first voltage and a second current corresponding to the second voltage are measured from the output terminal. The first voltage and the bias voltage have the same voltage levels. An output resistor value of the inverter is obtained according to the first and second voltages and the first and second currents. The transconductance of the oscillating circuit is obtained according to the output resistor value.

Abstract: An ESD prevention circuit is provided. The ESD prevention circuit comprises a voltage source, a charge-blocking unit, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, and an output unit. The charge-blocking unit is coupled to the voltage source and provides a reverse voltage to control the voltage source to remain at a zero potential when an electrostatic voltage is being generated. The first PMOS transistor is coupled to the charge-blocking unit. The first NMOS transistor is coupled to the first PMOS transistor. The second NMOS transistor is coupled to the first PMOS transistor and the first NMOS transistor. The output unit is coupled to the second NMOS transistor. The electrostatic voltage is affected by the charge-blocking unit and does not raise impendence of the turned-on second NMOS transistor.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a first metal-oxide-semiconductor (MOS), a second MOS, a first semiconductor region, and a second semiconductor region. The first and the second MOSs are formed on the substrate. The first semiconductor region is formed between the substrate and the first MOS. The second semiconductor region is formed between the substrate and the second MOS. The first semiconductor region and the second semiconductor region isolate the first MOS from the second MOS.