Patents by Inventor Minehiro Nemoto
Minehiro Nemoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030231009Abstract: A reliable uninterruptible DC power supply device. The DC backup power supply device includes an AC/DC converter, a DC/DC converter, voltage step-up/down choppers and a battery connected to a DC path of a main circuit connected with a load via a switching means, and a microcomputer. In the device, under control of the microcomputer, the voltage step-up/down choppers are first operated under a condition that the MOS FET was turned OFF for self diagnosis of the backup power supply device. Next, the switching means is turned ON to execute the remaining self diagnosis. The DC backup power supply device can execute its self diagnosis with a lessened likelihood of danger of exerting an adverse effect on the main circuit and also can exhibit a reliable uninterruptible power supply function.Type: ApplicationFiled: April 14, 2003Publication date: December 18, 2003Inventors: Minehiro Nemoto, Akihiko Kanouda, Fumikazu Takahashi, Masahiro Hamaogi, Yoshihide Takahashi, Takashi Tanabe, Takao Gotou, Masato Isogai, Toshikatsu Miyata
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Publication number: 20030222618Abstract: A DC backup power supply system having a battery; a charge-discharge circuit for charging and discharging a power between the battery and a DC line; and a control circuit for controlling the charge-discharge circuit, wherein the battery has a number of battery cells and cylindrical portions of the battery cells are laid on an approximately horizontal plane.Type: ApplicationFiled: April 14, 2003Publication date: December 4, 2003Inventors: Akihiko Kanouda, Minehiro Nemoto, Fumikazu Takahashi, Masahiro Hamaogi, Yoshihide Takahashi, Takashi Tanabe, Takao Gotou, Masato Isogai, Toshikatsu Miyata
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Publication number: 20030201523Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.Type: ApplicationFiled: May 22, 2003Publication date: October 30, 2003Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Publication number: 20030169808Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.Type: ApplicationFiled: March 4, 2003Publication date: September 11, 2003Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Patent number: 6611051Abstract: Wire bonding or printed wiring board leads or, alternatively, lead frames or equivalents thereof are used to electrically connect external electrodes of high withstand voltage capacitors formed on a plurality of semiconductor chips. A driver circuit for signal transmission or receiver circuit for signal receipt formed on the semiconductor chips are electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing the plurality of semiconductor chips to be received within either a single package or a single module. Using this arrangement, a semiconductor device is capable of achieving both dielectricity and size reduction.Type: GrantFiled: September 28, 2001Date of Patent: August 26, 2003Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Patent number: 6603807Abstract: An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.Type: GrantFiled: February 26, 1999Date of Patent: August 5, 2003Assignee: Hitachi, Ltd.Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Patent number: 6476750Abstract: The hardware of an over-sampling A/D and D/A converter is provided, which hardware is capable of being operated with either kind of software: one corresponding to a first method in which the over-sampling ratio is fixed and the other corresponding to a second method in which the over-sampling ratio is variable. The value N3 written on the pseudo-frequency-dividing-ratio-register 11 and the value N4 written on the pseudo-over-sampling-ratio-register 21 are converted through a user interface into the frequency dividing ratio N1 by the conversion circuit 12 and the converted result is written in the frequency-dividing-ratio-register 10.Type: GrantFiled: February 9, 2000Date of Patent: November 5, 2002Assignee: Hitachi, Ltd.Inventors: Nobuyasu Kanekawa, Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Kazuhisa Takami, Takayuki Iwasaki, Yusuke Takeuchi, Katsuhiro Furukawa
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Publication number: 20020125555Abstract: Wire bonding or printed wiring board leads or alternatively lead frames or equivalents thereof are used to electrically connect among external electrodes of high withstand voltage capacitors as formed on a plurality of semiconductor chips. A driver circuitry for signal transmission or receiver circuitry for signal receipt being formed on the semiconductor chips is electrically connected with substrate-side electrodes of said high withstand voltage capacitors, causing said plurality of semiconductor chips to be received within either a single package or a single module. Whereby a semiconductor device is capable of achieving both dielectricity and size reduction.Type: ApplicationFiled: September 28, 2001Publication date: September 12, 2002Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
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Patent number: 6445055Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor 11d in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 11a to 11d can increase the withstand voltage of a semiconductor integrated circuit.Type: GrantFiled: August 9, 2001Date of Patent: September 3, 2002Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Takayuki Iwasakii, Yusuke Takeuchi, Yoshiaki Yuyama, Shinichi Tanabe, Koki Sakai, Minehiro Nemoto, Seigo Yukutake, Yasuyuki Kojima, Atsuo Watanabe, Mitsuaki Horiuchi
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Publication number: 20020117750Abstract: In a semiconductor device, an imbedded insulating layer is formed in a semiconductor substrate. A plurality of electric circuits are formed on the imbedded insulating layer so as to be insulated each other, and are capacitively coupled through the semiconductor substrate. Wiring layers are formed on the electric circuits, and include inside electrodes which are capacitively coupled to the electric circuits. The electric circuits are connected through capacitors which are formed through the semiconductor substrate, and through capacitors which are formed through the electrodes.Type: ApplicationFiled: September 28, 2001Publication date: August 29, 2002Inventors: Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Nobuyasu Kanekawa, Noboru Akiyama
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Patent number: 6407432Abstract: A small sized semiconductor device having a high insulating performance between a primary side circuit and a secondary side circuit is realized. A circuit region 2, plural first and second terminal electrodes 5 connected to the circuit region 3, and an insulation-separation region 4 for separating electrically the first terminal electrodes from the second terminal electrodes, and for transmitting signals between the first and the second terminal electrodes are formed onto a semiconductor chip 1, and the insulation-separation region 4 is provided between the first and second terminal electrodes. The interval between the first and the second terminal electrodes on the same semiconductor chip can be separated with high insulating performance.Type: GrantFiled: December 29, 1999Date of Patent: June 18, 2002Assignee: Hitachi, Ltd.Inventors: Minehiro Nemoto, Yasuyuki Kojima, Nobuyasu Kanekawa, Seigou Yukutake, Katsuhiro Furukawa
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Publication number: 20020017686Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor lid in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 1a to 11d can increase the withstand voltage of a semiconductor integrated circuit.Type: ApplicationFiled: August 9, 2001Publication date: February 14, 2002Inventors: Takayuki Iwasakii, Yusuke Takeuchi, Yoshiaki Yuyama, Shinichi Tanabe, Koki Sakai, Minehiro Nemoto, Seigo Yukutake, Yasuyuki Kojima, Atsuo Watanabe, Mitsuaki Horiuchi
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Patent number: 6344809Abstract: In order to reduce the consumption of power of an isolator interface and an ADC, it is proposed to operate a calling signal reception or Caller ID signal reception function only with power supplied from the system switch while maintaining the on-hook condition of a telephone. At the time of normal operation, the output of the analogue digital converter is input to an isolator through the isolator interface, and at the time of the calling signal reception or the caller identification information reception, the output of the analogue digital converter is input directly to the isolator.Type: GrantFiled: November 3, 2000Date of Patent: February 5, 2002Assignee: Hitachi, Ltd.Inventors: Nobuyasu Kanekawa, Yasuyuki Kojima, Seigou Yukutake, Minehiro Nemoto, Kazuhisa Takami, Takayuki Iwasaki, Yusuke Takeuchi, Yasuo Shima
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Patent number: 6040827Abstract: A driver circuit wherein a first switching element and a second switching element are totem-pole-connected, wherein the totem pole connection is connected at its one end, node and other end with a power source, an output to a load and a reference potential, respectively, wherein the first switching element is connected between the one end and the node, wherein the second switching element is connected between the node and the other end, and wherein a third switching element is connected between the one end of the totem pole connection and the control terminal of the first switching element.Type: GrantFiled: July 10, 1997Date of Patent: March 21, 2000Assignees: Hitachi, Ltd., Hitachi Haramachi Electronics Co., Ltd.Inventors: Kazuhiro Shiina, Koji Kawamoto, Masato Miura, Hitoshi Ohura, Shoichi Ozeki, Noboru Akiyama, Kunihoro Nunomura, Minehiro Nemoto, Masahiro Iwamura
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Patent number: 5777865Abstract: A power conversion apparatus has a four terminal semiconductor device including a drain terminal and a source terminal for supplying main current, a gate terminal for controlling the main current, and a base terminal for controlling the on-state voltage, and energy storage means which is connected in the main current circuit consisting of a load and a main power source, wherein electric power is supplied to the base terminal of the semiconductor device by energy stored in the storage means.Because electric power supplied to the base terminal is provided by energy from the main current circuit, the occurrence of power loss in the control circuit to achieve high frequency operation is avoided.Type: GrantFiled: August 15, 1995Date of Patent: July 7, 1998Assignee: Hitachi, Ltd.Inventors: Minehiro Nemoto, Hideki Miyazaki, Yoshitaka Sugawara