Abstract: A data input circuit provided in a data processing equipment is disclosed. The input circuit includes a timing circuit generating a latch pulse in asynchronism with a read request signal generated by a CPU and a latch circuit latching input data in response to the latch pulse. The data latched in the latch circuit is transferred to a data bus in response to the read request signal. The input circuit further includes circuitry responsive to an access by the CPU for delaying the generation of the latch pulse such that the latch pulse is generated after the CPU stops to generate the read request signal. The latch circuit is thereby prevented from latching the input data while the read request signal is generated.

Abstract: A timer/counter comprising an operation controller coupled to receive a control information for generating control signals for a selected operation, and a register block coupled to a bus and including a plurality of count registers, a corresponding number of timer registers storing various set values and a buffer circuit controlled by the operation controller to sequentially read data from one of the count registers to the bus and then write the data on the bus to the same count register. An incrementer is coupled to the bus and controlled by the operation controller to increment the data on the bus and to output an incremented data to the bus. A coincidence flag coupled to the register block is set when the incremented data in a count register of the timer block has coincided with a value stored in a corresponding timer register. A clear controller coupled to the coincidence flag clears the count register having the count value in coincidence with the value of the corresponding timer register.

Abstract: A data processing apparatus includes an interruption control unit having an associative memory which is used to store a priority data of an interruption and a mode data designating an interruption operation mode. A sequential scanning data is applied according to a priority order to the associative memory. Thus, the mode data required to operate the interruption can be selected and transferred to an interruption processing unit by comparing the stored priority data with the applied scanning data in the associative memory without control of a central processing unit.

Abstract: A pulse generator for use in a digital/analog converter which generates a pulse train with pulse widths modulated in accordance with an input digital signal. The leading edge of an arbitrary pulse in the pulse train is widened by one half of a clock period and the trailing edge of another pulse is widened by one half of the clock period, in accordance with the input digital signal.