Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n?1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n?1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.

Abstract: Data transfer equipment enables high-speed transfer between a DTE (Data Terminal Equipment) and a DCE (Data Circuit Terminating Equipment). The data transfer equipment serves the DCE, and is connected through a first parallel bus to the DTE, and has a data processing section used to process data to be exchanged with the DTE. The data transfer equipment is provided with a transfer processing section connected to the data processing section through a second parallel bus, which is adapted to transfer, based on a specified control procedure, data received through the first parallel bus from the DTE to the data processing section through the second parallel bus and to transfer, based on the control procedures, data received through the second parallel bus from the data processing section to the DTE.

Abstract: Data transfer equipment is provided which enables high-speed transfer between a DTE (Data Terminal Equipment) and a DCE (Data Circuit Terminating Equipment).

Abstract: A data register which outputs an input data as is when the input data fulfills a set data width for outputting, and holds the input data until a bit width of the input data is equal to or more than the set data width, in response to a first enable signal. A first selector which selects an n-bit byte lane from a (2n-1)-bit byte lane of the data register in response to a first select signal, and a second selector which selects an n-bit byte lane out of a (2n-1)-bit byte lane and outputs a valid data in response to a second select signal. A data buffer which receives and stores the valid data in response to a second enable signals.