Patents by Inventor Mineo Gotou

Mineo Gotou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4948979
    Abstract: A vacuum device comprises a vacuum working chamber for performing a predetermined process to a material such as substrate and a vacuum prechamber for changing the material. Both the vacuum chambers are coupled by a coupling member so as to communicate the interiors of the respective chambers and the communcation is managed by valve means located for the coupling member. Both vacuum chambers may be constructed so as to be movable or pivotable horizontally with respect to each other. The coupling member may be constructed as an independent member which is inserted between both the vacuum chambers as occasion demands.
    Type: Grant
    Filed: December 21, 1988
    Date of Patent: August 14, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Munakata, Mineo Gotou
  • Patent number: 4728797
    Abstract: The data in a counter in which a tolerable displacement of a table during the drawing in a sub-field and a movement of the table are compared in comparator. When the table movement exceeds a predetermined tolerable displacement preset in circuit for table movement correction, a signal for interrupting the pattern drawing is transferred to a control section. The main deflection position and the correction data for minor deflection distortion are set anew by a computer. Then, drawing of the remaining patterns is restarted.
    Type: Grant
    Filed: December 19, 1986
    Date of Patent: March 1, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mineo Gotou, Hideo Kusakabe
  • Patent number: 4636968
    Abstract: A method of positioning a beam to a specific portion of a semiconductor wafer is disclosed. In this method, the positions of two positioning marks formed on the wafer are measured. The position of another of the marks is calculated. Then, an actual position of the mark is measured. The calculated position and the actual position are compared with each other. It is judged whether or not the mark satisfies a predetermined condition. When the mark satisfies the predetermined condition, the specific portion of the semiconductor wafer is determined using the actual position of the mark. When it does not satisfy the predetermined condition, the specific area is determined using the position calculated using the positions of the marks around the mark.
    Type: Grant
    Filed: June 28, 1984
    Date of Patent: January 13, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mineo Gotou, Hirotsugu Wada
  • Patent number: 4621371
    Abstract: A method of forming by projection an integrated circuit pattern on a first semiconductor wafer, wherein a plurality of reference marks are projected onto a second semiconductor wafer by the irradiation of radiant rays from a projector apparatus used to form the integrated circuit pattern onto the first semiconductor wafer. The positions of the reference marks projected onto the second semiconductor wafer are measured, thereby measuring the projection distortion peculiar to the projector apparatus. As the next step, a projection mask used to form the integrated circuit pattern is produced with the use of the measured projection distortions which has a distortion opposite that of the projector so as to offset its projection distortion. The mark is mounted in the projector apparatus, and the radiant rays are irradiated onto the mask thus projecting the integrated circuit pattern onto the first semiconductor wafer.
    Type: Grant
    Filed: March 29, 1984
    Date of Patent: November 4, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Mineo Gotou, Shunichi Sano
  • Patent number: 4558225
    Abstract: Disclosed is a method for measuring the position of a silicon wafer as a workpiece to be exposed. The method is suitably used in an electron beam exposure system. A wafer has a plurality of chip alignment marks which respectively designate a plurality of chip field areas, included in a dicing line area. When the wafer is contained ion a holder and is fixed in the exposure system, edge portions of the wafer are partially scanned with the electron beam to roughly measure the position of the wafer. In accordance with this wafer position data, a wafer surface portion required for detecting only the marks is defined within the dicing line area. In the mark detection with the electron beam, the electron beam irradiates only the defined wafer surface portion of the wafer surface, thereby providing highly precise measurement of the wafer position and avoiding undesirable irritation of the circuit formation area.
    Type: Grant
    Filed: August 29, 1983
    Date of Patent: December 10, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Mineo Gotou, Ryoichi Yoshikawa, Toru Tojo, Hirotsugu Wada