Patents by Inventor Mineo Miura

Mineo Miura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321451
    Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Application
    Filed: June 18, 2020
    Publication date: October 8, 2020
    Inventors: Keiji OKUMURA, Mineo MIURA, Yuki NAKANO, Noriaki KAWAMOTO, Hidetoshi ABE
  • Patent number: 10727318
    Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 28, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Keiji Okumura, Mineo Miura, Yuki Nakano, Noriaki Kawamoto, Hidetoshi Abe
  • Publication number: 20170092743
    Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 30, 2017
    Applicant: ROHM CO., LTD.
    Inventors: Keiji OKUMURA, Mineo MIURA, Yuki NAKANO, Noriaki KAWAMOTO, Hidetoshi ABE
  • Patent number: 9472688
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer, a trench formed selectively in an obverse surface portion of the semiconductor layer and defining a unit cell of predetermined shape in the obverse surface portion, a second conductivity type layer formed to conform to a portion or an entirety of an inner surface of the trench, an obverse surface layer of a first conductivity type formed so as to be exposed from an obverse surface of the semiconductor layer in the unit cell, a reverse surface layer of the first conductivity type formed so as to be exposed from a reverse surface of the semiconductor layer, a drift layer of the first conductivity type formed between the obverse surface layer and the reverse surface layer of the semiconductor layer and being of lower concentration than the obverse surface layer and the reverse surface layer, a first electrode contacting the obverse surface layer and forming an ohmic contact with the obverse surface layer, and a second elect
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: October 18, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Mineo Miura
  • Patent number: 9461533
    Abstract: When an overcurrent is detected by an overcurrent detecting circuit (36), a first switch circuit (32) selects a second input terminal (b) and connects an output terminal (c) to the second input terminal (b), with the result that the output terminal (c) of the first switch circuit (32) is put into a high-impedance state. The second switch circuit (34) selects a second output terminal (f) and connects an input terminal (d) to the second output terminal (f), with the result that the input terminal (d) of the second switch circuit (34) is grounded. That is, the gate of a first MOSFET (21) is grounded via a current interrupting resistor (35).
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: October 4, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Masashi Hayashiguchi, Mineo Miura, Kazuhide Ino
  • Publication number: 20160005884
    Abstract: A semiconductor device according to the present invention includes a semiconductor layer, a trench formed selectively in an obverse surface portion of the semiconductor layer and defining a unit cell of predetermined shape in the obverse surface portion, a second conductivity type layer formed to conform to a portion or an entirety of an inner surface of the trench, an obverse surface layer of a first conductivity type formed so as to be exposed from an obverse surface of the semiconductor layer in the unit cell, a reverse surface layer of the first conductivity type formed so as to be exposed from a reverse surface of the semiconductor layer, a drift layer of the first conductivity type formed between the obverse surface layer and the reverse surface layer of the semiconductor layer and being of lower concentration than the obverse surface layer and the reverse surface layer, a first electrode contacting the obverse surface layer and forming an ohmic contact with the obverse surface layer, and a second elect
    Type: Application
    Filed: December 25, 2013
    Publication date: January 7, 2016
    Inventors: Masatoshi AKETA, Mineo MIURA
  • Publication number: 20150311779
    Abstract: When an overcurrent is detected by an overcurrent detecting circuit (36), a first switch circuit (32) selects a second input terminal (b) and connects an output terminal (c) to the second input terminal (b), with the result that the output terminal (c) of the first switch circuit (32) is put into a high-impedance state. The second switch circuit (34) selects a second output terminal (f) and connects an input terminal (d) to the second output terminal (f), with the result that the input terminal (d) of the second switch circuit (34) is grounded. That is, the gate of a first MOSFET (21) is grounded via a current interrupting resistor (35).
    Type: Application
    Filed: October 30, 2013
    Publication date: October 29, 2015
    Inventors: Masashi HAYASHIGUCHI, Mineo MIURA, Kazuhide INO
  • Patent number: 9136378
    Abstract: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: September 15, 2015
    Assignee: ROHM CO., LTD.
    Inventors: Keiji Okumura, Mineo Miura, Katsuhisa Nagao, Shuhei Mitani
  • Patent number: 9048103
    Abstract: A method for producing a semiconductor device (20) is disclosed. The semiconductor device (20) includes: 1) a semiconductor substrate (1, 2), 2) a hetero semiconductor area (3) configured to contact a first main face (1A) of the semiconductor substrate (1, 2) and different from the semiconductor substrate (1, 2) in band gap, 3) a gate electrode (7) contacting, via a gate insulating film (6), a part of a junction part (13) between the hetero semiconductor area (3) and the semiconductor substrate (1, 2), 4) a source electrode (8) configured to connect to the hetero semiconductor area (3), and 5) a drain electrode (9) configured to make an ohmic connection with the semiconductor substrate (1, 2). The method includes the following sequential operations: i) forming the gate insulating film (6); and ii) nitriding the gate insulating film (6).
    Type: Grant
    Filed: June 26, 2006
    Date of Patent: June 2, 2015
    Assignees: NISSAN MOTOR CO., LTD., ROHM CO., LTD.
    Inventors: Yoshio Shimoida, Hideaki Tanaka, Tetsuya Hayashi, Masakatsu Hoshi, Shigeharu Yamagami, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura, Takashi Nakamura
  • Patent number: 8901571
    Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: December 2, 2014
    Assignee: Rohm Co., Ltd.
    Inventors: Yuki Nakano, Shuhei Mitani, Mineo Miura
  • Patent number: 8884309
    Abstract: An AC switch includes a first compound semiconductor MOSFET and a second compound semiconductor MOSFET whose sources are connected with each other, a first output terminal connected to the drain of the first compound semiconductor MOSFET, and a second output terminal connected to the drain of the second compound semiconductor MOSFET. The withstand voltage between the first output terminal and the second output terminal in an off state is not less than 400 V. The resistance between the first output terminal and the second output terminal in an on state is not more than 20 m?.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: November 11, 2014
    Assignee: Rohm Co., Ltd.
    Inventor: Mineo Miura
  • Patent number: 8722497
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 13, 2014
    Assignees: Nissan Motor Co., Ltd., Rohm Co., Ltd.
    Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
  • Patent number: 8716087
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: May 6, 2014
    Assignees: Nissan Motor Co., Ltd., Rohm Co., Ltd.
    Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
  • Publication number: 20140054611
    Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type; source regions of the first conductivity type, formed on a surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film. In the semiconductor layer, trenches extending between two neighboring source regions are formed, the inside surface of the trenches are covered by a gate insulating film, and the gate electrodes comprise surface-facing parts, which are buried in the trenches.
    Type: Application
    Filed: August 27, 2013
    Publication date: February 27, 2014
    Applicant: ROHM CO., LTD.
    Inventors: Yuki NAKANO, Shuhei MITANI, Mineo MIURA
  • Publication number: 20130309877
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Application
    Filed: July 29, 2013
    Publication date: November 21, 2013
    Applicants: ROHM CO., LTD., NISSAN MOTOR CO., LTD.
    Inventors: Satoshi TANIMOTO, Noriaki KAWAMOTO, Takayuki KITOU, Mineo MIURA
  • Publication number: 20130309859
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (0) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Application
    Filed: July 29, 2013
    Publication date: November 21, 2013
    Applicants: ROHM CO., LTD., NISSAN MOTOR CO., LTD.
    Inventors: Satoshi TANIMOTO, Noriaki KAWAMOTO, Takayuki KITOU, Mineo MIURA
  • Patent number: 8546814
    Abstract: A semiconductor device including a semiconductor layer of a first conductivity type; a plurality of body regions of a second conductivity type, each formed in a region extending from the surface of the semiconductor layer to a halfway portion of the same in the thickness direction, and each spaced apart from each other in a direction perpendicular to the thickness direction; source regions of the first conductivity type, each formed on the surface layer part of each body region and spaced away from the edges of each body region; a gate insulating film formed on the semiconductor layer; and gate electrodes formed on the gate insulating film.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: October 1, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Yuki Nakano, Shuhei Mitani, Mineo Miura
  • Publication number: 20130248981
    Abstract: A semiconductor device includes a first conductive-type semiconductor layer, a second conductive-type body region formed in a surficial portion of the semiconductor layer, a first conductive-type source region formed in a surficial portion of the body region, a gate insulating film provided on the semiconductor layer and containing nitrogen atoms, the gate insulating film including a first portion in contact with the semiconductor layer outside the body region, a second portion in contact with the body region, and a third portion in contact with the source region, and a gate electrode provided on the gate insulating film in an area extending across the semiconductor layer outside the body region, the body region, and the source region. The third portion of the gate insulating film has a thickness greater than the thickness of the first portion and the thickness of the second portion.
    Type: Application
    Filed: September 15, 2011
    Publication date: September 26, 2013
    Applicant: ROHM CO., LTD.
    Inventors: Keiji Okumura, Mineo Miura, Katsuhisa Nagao, Shuhei Mitani
  • Patent number: 8497218
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: July 30, 2013
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Satoshi Tanimoto, Noriaki Kawamoto, Takayuki Kitou, Mineo Miura
  • Publication number: 20130009256
    Abstract: The semiconductor device according to the present invention includes a semiconductor layer of a first conductivity type, body regions of a second conductivity type plurally formed on a surface layer portion of the semiconductor layer at an interval, a source region of the first conductivity type formed on a surface layer portion of each body region, a gate insulating film provided on the semiconductor layer to extend between the body regions adjacent to each other, a gate electrode provided on the gate insulating film and opposed to the body regions, and a field relaxation portion provided between the body regions adjacent to each other for relaxing an electric field generated in the gate insulating film.
    Type: Application
    Filed: March 30, 2011
    Publication date: January 10, 2013
    Applicant: ROHM CO LTD
    Inventors: Keiji Okumura, Mineo Miura, Yuki Nakano, Noriaki Kawamoto