Patents by Inventor Minesh A. Patel

Minesh A. Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of creating hydrogen isotope reservoirs in a semiconductor device
    Patent number: 6605529
    Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.
    Type: Grant
    Filed: May 11, 2001
    Date of Patent: August 12, 2003
    Assignee: Agere Systems Inc.
    Inventors: Sundar Chetlur, Jennifer M. McKinley, Minesh A. Patel, Pradip K. Roy, Jonathan Zhong-Ning Zhou
  • Method of creating hydrogen isotope reservoirs in a semiconductor device
    Publication number: 20020168841
    Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.
    Type: Application
    Filed: May 11, 2001
    Publication date: November 14, 2002
    Inventors: Sundar Chetlur, Jennifer M. McKinley, Minesh A. Patel, Pradip K. Roy, Jonathan Zhong-Ning Zhou
  • Method of determining a trap density of a semiconductor/oxide interface by a contactless charge technique
    Patent number: 6391668
    Abstract: The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.
    Type: Grant
    Filed: May 1, 2000
    Date of Patent: May 21, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Carlos M. Chacon, Sundar S. Chetlur, Brian E. Harding, Minesh A. Patel, Pradip K. Roy