Abstract: The present disclosure relates to a data processing device comprising means configured for adapting a regulated digital platform, the data processing device (120) being arranged to monitor and adapt said digital platform (110); obtain user profile data (121) indicative of interactions with said digital platform (110) associated with a user profile (111); determine a set of platform risk values (122) based on the obtained user profile data (121) and said digital platform (110), wherein said set of platform risk values (122) is indicative of at least one risk associated with said digital platform (110) for said user profile (111); and adapt said digital platform (110) for at least said user profile (111) based on the determined set of platform risk values (122), and/or determine a set of aggregate platform risk values for the digital platform (110) based on at least the determined set of platform risk values (122).

Abstract: The present invention is in the field of molecular biology and relates to improved methods for plant transformation and to polynucleotides and polypeptides for achieving the same.

Abstract: A battery energy storage system comprises a first equipment unit comprising a first skid positionable on a surface, a first inverter and a first transformer mounted on the first skid, a second equipment unit comprising a second skid, a second inverter and a second transformer mounted on the second skid, and a support structure for positioning the second equipment unit longitudinally above and spaced apart from the first equipment unit in a laterally offset manner. A method of increasing energy storage capacity of a storage system comprises building a support structure over a first inverter and transformer unit installed at a first location, placing a second inverter and transformer unit on the support structure such that the second inverter and transformer unit is longitudinally spaced from and laterally offset from the first inverter and transformer unit and adding an additional battery container.

Abstract: A breastfeeding simulation system (BSS). The BSS includes a breast prosthesis having a pliable nipple, and a baby mannequin configured to interface with the breast prosthesis, the baby mannequin includes an articulating head, a motorized jaw, the articulating head further includes a mouth normally placed in a closed position by the motorized jaw, where the motorized jaw opens when an object is detected near the mouth and the baby mannequin is positioned according to a predetermined angular position, and a palate sensor, configured to provide a proper placement signal when the pliable nipple is placed at a predetermined position.

Abstract: A breastfeeding simulation system (BSS). The BSS includes a breast prosthesis having a pliable nipple, and a baby mannequin configured to interface with the breast prosthesis, the baby mannequin includes an articulating head, a motorized jaw, the articulating head further includes a mouth normally placed in a closed position by the motorized jaw, where the motorized jaw opens when an object is detected near the mouth and the baby mannequin is positioned according to a predetermined angular position, and a palate sensor, configured to provide a proper placement signal when the pliable nipple is placed at a predetermined position.

Abstract: An outdoor enclosure for electronic equipment is described. A shroud mounted around the enclosure provides a plenum for external air, as well as protection from solar loading. A fan located inside the equipment enclosure circulates the air inside the equipment enclosure downward along the sides of the enclosure to accomplish heat exchange with external air. Another fan draws external air upwardly across the surfaces of the equipment enclosure. The heated external air is exhausted at the top of the shroud.

Abstract: A data processing system including a processor having a load/store unit and method for utilizing alias hit signals to detect errors within the read address tag arrays. Within a load store unit, implemented within a processor, a real address tag array is utilized to indicate when effective address aliasing occurs in a primary cache array. If aliasing occurs, Alias Hit signals are then used to clear any aliased entries. These Alias Hit signals can also be utilized to determine if there has been some type of failure within the real address tag array.

Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

Abstract: The present invention provides a method of determining a trap density of a semiconductor substrate/dielectric interface. In one embodiment, the method comprises measuring a current within a semiconductor substrate resulting from a flow of carriers from traps located near the interface, wherein the measured current is a function of the number of traps located at the interface, and determining the trap density as a function of the measured current.

Abstract: A silicon-on-insulator digital circuit combination having a body voltage control stage and a voltage clamp stage. The body voltage control stage is responsive to an input control signal to provide an output driver signal. The body voltage control stage has a first transistor with a terminal for electrically-coupling to a combinational logic circuit, and a body contact electrically-coupled to the input control signal such that a threshold voltage of the transistor is reduced when the transistor is placed in an active state. It can be readily appreciated that the reduced threshold voltage of the transistor increases the transition rate for the first transistor to an inactive state in response to the input control signal. The voltage clamp stage has a second transistor responsive to the input control signal such that the terminal is electrically-coupled to a reference voltage when the first transistor is in the inactive state.

Abstract: A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharge transistor, multiple input transistors, and a supplemental precharge transistor. Connected to a power supply, the precharge transistor receives a clock input. The discharge transistor is connected to ground and also receives the clock input. The input transistors, which are coupled between the precharge transistor and the discharge transistor, each receives a signal input. The supplemental precharge transistor is connected to the power supply and to a body of each of the input transistors. The supplemental precharge transistor also receives the same clock input as the precharge transistor.

Abstract: A multi-threaded memory (and associated method) for use in a multi-threaded computer system in which plural threads are used with a single processor. The multi-threaded memory includes: multi-threaded storage cells; at least one write decoder supplying information to a selected multi-threaded storage cell; and at least one read decoder accessing information from a selected multi-threaded storage cell. Each of the multi-threaded storage cells includes: N storage elements, where N.gtoreq.2, each of the N storage elements having a thread-correspondent content; a write interface supplying information to the intra-cell storage elements; and a read interface reading information from the intra-cell storage elements. At least one of the intra-cell read and write interfaces selects one of the thread-correspondent contents based at least in part by identifying the corresponding thread to achieve intra-cell thread-correspondent content selection.