Patents by Inventor Minesh Amrat Patel

Minesh Amrat Patel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6940151
    Abstract: A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1.5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 6, 2005
    Assignee: Agere Systems, Inc.
    Inventors: Michael Scott Carroll, Yi Ma, Minesh Amrat Patel, Peyman Sana
  • Publication number: 20040061179
    Abstract: A low-thermal budget, silicon-rich silicon nitride film may include a concentration of hydrogen in Si—H bonds being at least 1.5 times as great as a concentration of hydrogen in N—H bonds. The silicon nitride film suppresses boron diffusion in boron-doped devices when such devices are processed using high-temperature processing operations that conventionally urge boron diffusion. The low-thermal budget, silicon-rich silicon nitride film may be used to form spacers in CMOS devices, it may be used as part of a dielectric stack to prevent shorting in tightly packed SRAM arrays, and it may be used in BiCMOS processing to form a base nitride layer and/or nitride spacers isolating the base from the emitter. Furthermore the low-thermal budget, silicon-rich silicon nitride film may remain covering the CMOS structure while bipolar devices are being formed, as it suppresses the boron diffusion that results in boron penetration and boron-doped poly depletion.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 1, 2004
    Inventors: Michael Scott Carroll, Yi Ma, Minesh Amrat Patel, Peyman Sana
  • Patent number: 6576522
    Abstract: A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: June 10, 2003
    Assignee: Agere Systems Inc.
    Inventors: Sundar Srinivasan Chetlur, Pradip Kumar Roy, Minesh Amrat Patel, Sidhartha Sen, Vivek Saxena
  • Publication number: 20030091870
    Abstract: A liner and method of forming a liner for a tungsten plug in a semiconductor device which reduces cost and improves reliability. In one aspect, it has been discovered that by depositing an initial film of titanium using any conventional process such as CVD, PVD or IMP (ion metal plasma) and then heating the device in a nitrogen atmosphere to a temperature of about 450 degrees C., a thin protective layer of titanium nitride can be form on the surface of the initial film. The protective layer has been found to be uniform in density and avoids the irregularities occurring in deposited titanium nitride. The thickness of the TiN layer can be controlled by controlling the time duration of the annealing process and by controlling the pressure of the nitrogen in the annealing tool. Using this two step method, the integrity of the titanium nitride layer is preserved and the formation of volcanoes is avoided.
    Type: Application
    Filed: November 15, 2001
    Publication date: May 15, 2003
    Inventors: Siddhartha Bhowmik, Sailesh Mansinh Merchant, Minesh Amrat Patel, Darrell L. Simpson
  • Publication number: 20020072187
    Abstract: A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Sundar Srinivasan Chetlur, Pradip Kumar Roy, Minesh Amrat Patel, Sidhartha Sen, Vivek Saxena