Patents by Inventor Mineyoshi Hasegawa
Mineyoshi Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11300733Abstract: An optical waveguide member connector kit includes an optical waveguide member including an optical waveguide and a connector accommodating the optical waveguide member. The connector includes a main body having a bottom wall, and a first wall and a second wall that extend from the bottom wall toward one side in a thickness direction of the bottom wall and face each other at spaced intervals therebetween, and a lid disposed between the first wall and the second wall and sandwiching the optical waveguide member with the bottom wall when the optical waveguide member is accommodated in the connector. A ratio (L1/L2) of a length L1 in a facing direction of the lid to a facing length L2 between the first wall and the second wall is 0.80 or more and 0.99 or less.Type: GrantFiled: October 19, 2018Date of Patent: April 12, 2022Assignee: NITTO DENKO CORPORATIONInventors: Naoto Konegawa, Yuichi Tsujita, Mineyoshi Hasegawa
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Publication number: 20200249400Abstract: An optical waveguide member connector kit includes an optical waveguide member including an optical waveguide and a connector accommodating the optical waveguide member. The connector includes a main body having a bottom wall, and a first wall and a second wall that extend from the bottom wall toward one side in a thickness direction of the bottom wall and face each other at spaced intervals therebetween, and a lid disposed between the first wall and the second wall and sandwiching the optical waveguide member with the bottom wall when the optical waveguide member is accommodated in the connector. A ratio (L1/L2) of a length L1 in a facing direction of the lid to a facing length L2 between the first wall and the second wall is 0.80 or more and 0.99 or less.Type: ApplicationFiled: October 19, 2018Publication date: August 6, 2020Applicant: NITTO DENKO CORPORATIONInventors: Naoto KONEGAWA, Yuichi TSUJITA, Mineyoshi HASEGAWA
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Patent number: 9288903Abstract: A plurality of conductor traces are formed on a porous base insulating layer made of porous ePTFE. Each conductor trace has a laminated structure of a seed layer and a conductor layer. A cover insulating layer is formed on the base insulating layer to cover each conductor trace. The ePTFE used as the porous base insulating layer has continuous pores. An average pore size of the ePTFE is not less than 0.05 ?m and not more than 1.0 ?m.Type: GrantFiled: April 27, 2011Date of Patent: March 15, 2016Assignee: NITTO DENKO CORPORATIONInventors: Mineyoshi Hasegawa, Keisuke Okumura, Shinichi Inoue, Hiroyuki Hanazono
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Patent number: 8822834Abstract: A printed circuit board includes a base insulating layer formed of a porous film. Conductor traces are formed on the base insulating layer formed of the porous film. A cover insulating layer is formed on the base insulating layer to cover the conductor traces. The porous film used as the base insulating layer has a reflectivity of not less than 50% for light of at least a part of wavelengths in a wavelength region from 400 nm to 800 nm.Type: GrantFiled: July 21, 2011Date of Patent: September 2, 2014Assignee: Nitto Denko CorporationInventors: Shinichi Inoue, Hiroyuki Hanazono, Mineyoshi Hasegawa
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Patent number: 8438726Abstract: A resist film is formed on a conductor layer of a two-layered base material composed of a carrier layer and the conductor layer. Next, the resist film is exposed and developed, so that an etching resist pattern is formed. A region of the conductor layer that is exposed while not covered with the etching resist pattern is removed by etching. A conductor pattern is formed by removing the etching resist pattern. Then, an adhesive layer precursor is applied on an entire surface including an upper surface of the conductor pattern. The adhesive layer precursor is exposed and developed, so that an adhesive pattern is formed on the conductor pattern. After that, a base insulating layer is joined onto the conductor pattern with the adhesive pattern sandwiched therebetween. Finally, a carrier layer is separated from the conductor pattern, so that the FPC board is manufactured.Type: GrantFiled: April 8, 2011Date of Patent: May 14, 2013Assignee: Nitto Denko CorporationInventors: Shinichi Inoue, Hiroyuki Hanazono, Mineyoshi Hasegawa, Keisuke Okumura
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Publication number: 20120024574Abstract: A printed circuit board includes a base insulating layer formed of a porous film. Conductor traces are formed on the base insulating layer formed of the porous film. A cover insulating layer is formed on the base insulating layer to cover the conductor traces. The porous film used as the base insulating layer has a reflectivity of not less than 50% for light of at least a part of wavelengths in a wavelength region from 400 nm to 800 nm.Type: ApplicationFiled: July 21, 2011Publication date: February 2, 2012Applicant: NITTO DENKO CORPORATIONInventors: Shinichi INOUE, Hiroyuki HANAZONO, Mineyoshi HASEGAWA
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Publication number: 20120024581Abstract: A plurality of conductor traces are formed on a porous base insulating layer made of porous ePTFE. Each conductor trace has a laminated structure of a seed layer and a conductor layer. A cover insulating layer is formed on the base insulating layer to cover each conductor trace. The ePTFE used as the porous base insulating layer has continuous pores. An average pore size of the ePTFE is not less than 0.05 ?m and not more than 1.0 ?m.Type: ApplicationFiled: April 27, 2011Publication date: February 2, 2012Applicant: NITTO DENKO CORPORATIONInventors: Mineyoshi HASEGAWA, Keisuke OKUMURA, Shinichi INOUE, Hiroyuki HANAZONO
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Publication number: 20110281202Abstract: An FPC board, electrode films and a fuel accommodating chamber are accommodated in a casing. In the FPC board, a plurality of collector portions are joined onto a base insulating layer with an adhesive pattern sandwiched therebetween. The base insulating layer is made of porous ePTFE, and is air-permeable. Openings are formed in the collector portions. The adhesive pattern has the same shape as the plurality of collector portions. The FPC board is sandwiched by an upper surface portion and a lower surface portion of the casing while being bent along a bend portion. The electrode films are arranged between the plurality of collector portions of the FPC board. The fuel accommodating chamber is provided between the FPC board and the lower surface portion so as to come in contact with the base insulating layer. A liquid fuel is supplied to the fuel accommodating chamber.Type: ApplicationFiled: April 29, 2011Publication date: November 17, 2011Applicant: NITTO DENKO CORPORATIONInventors: Hiroyuki HANAZONO, Shinichi INOUE, Mineyoshi HASEGAWA, Keisuke OKUMURA, Hirofumi EBE
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Publication number: 20110277321Abstract: A resist film is formed on a conductor layer of a two-layered base material composed of a carrier layer and the conductor layer. Next, the resist film is exposed and developed, so that an etching resist pattern is formed. A region of the conductor layer that is exposed while not covered with the etching resist pattern is removed by etching. A conductor pattern is formed by removing the etching resist pattern. Then, an adhesive layer precursor is applied on an entire surface including an upper surface of the conductor pattern. The adhesive layer precursor is exposed and developed, so that an adhesive pattern is formed on the conductor pattern. After that, a base insulating layer is joined onto the conductor pattern with the adhesive pattern sandwiched therebetween. Finally, a carrier layer is separated from the conductor pattern, so that the FPC board is manufactured.Type: ApplicationFiled: April 8, 2011Publication date: November 17, 2011Applicant: NITTO DENKO CORPORATIONInventors: Shinichi INOUE, Hiroyuki HANAZONO, Mineyoshi HASEGAWA, Keisuke OKUMURA
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Patent number: 7281327Abstract: An insulating substrate with metal foils on both sides thereof is prepared, and a through hole that passes through the metal foils and insulating substrate is formed. An electroless copper plating layer is formed on an inner surface of the through hole and a surface of each of the metal foils, followed by the formation of an electrolytic copper plating layer on the overall surface of the electroless copper plating layer. After removing the electrolytic copper plating layer except the portions on the inner surface and a peripheral region of the through hole, the metal foils are processed to form conductor patterns.Type: GrantFiled: May 5, 2005Date of Patent: October 16, 2007Assignee: Nitto Denko CorporationInventors: Yuichi Takayoshi, Mineyoshi Hasegawa, Yasushi Tsuda, Akinori Itokawa
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Publication number: 20060016072Abstract: An insulating substrate with metal foils on both sides thereof is prepared, and a through hole that passes through the metal foils and insulating substrate is formed. An electroless copper plating layer is formed on an inner surface of the through hole and a surface of each of the metal foils, followed by the formation of an electrolytic copper plating layer on the overall surface of the electroless copper plating layer. After removing the electrolytic copper plating layer except the portions on the inner surface and a peripheral region of the through hole, the metal foils are processed to form conductor patterns.Type: ApplicationFiled: May 5, 2005Publication date: January 26, 2006Inventors: Yuichi Takayoshi, Mineyoshi Hasegawa, Yasushi Tsuda, Akinori Itokawa
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Patent number: 6902949Abstract: First and second metal foil layers are laminated on opposite surfaces of a first insulating layer to form a first board. Then, the first and second metal foil layers are formed into predetermined conductor patterns respectively. Then, second and third insulating layers of second and third boards formed separately from the first board are laminated on the first and second metal foil layers through first and second adhesive layers respectively. Then, a thin layer portion is removed and thick layer portions are formed into predetermined conductor patterns respectively in third and fourth metal foil layers of the second and third boards.Type: GrantFiled: April 1, 2002Date of Patent: June 7, 2005Assignee: Nitto Denko CorporationInventors: Hiroshi Yamazaki, Mineyoshi Hasegawa, Satoshi Tanigawa
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Patent number: 6887560Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.Type: GrantFiled: July 3, 2002Date of Patent: May 3, 2005Assignee: Nitto Denko CorporationInventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
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Publication number: 20050079652Abstract: A method of producing a multilayer wired circuit board that can suppress making gouge in an adhesive layer when a hole is formed by irradiation with a laser beam, to provide a smoothened inside surface of the hole so as to provide enhanced reliability of electrical connection. A first substrate 4 having the structure wherein a first metal foil 2 and a second metal foil 3 are formed on both sides of a first insulating layer 1 and a second substrate 7 having the structure wherein a third metal foil 6 is formed on a single side of a second insulating layer 5 are prepared, separately. Then, the first metal foil 2 of the first substrate 4 and the second insulating layer 5 of the second substrate 7 are bonded together through an adhesive layer 8. Thereafter, the resultant laminate is irradiated with a laser beam emitting from the first substrate 4 side toward the second substrate 7 side, to form a through hole 9.Type: ApplicationFiled: October 7, 2004Publication date: April 14, 2005Inventors: Mineyoshi Hasegawa, Kei Nakamura, Toshikazu Baba
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Publication number: 20040035520Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.Type: ApplicationFiled: March 5, 2003Publication date: February 26, 2004Inventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
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Publication number: 20020140076Abstract: First and second metal foil layers are laminated on opposite surfaces of a first insulating layer to form a first board. Then, the first and second metal foil layers are formed into predetermined conductor patterns respectively. Then, second and third insulating layers of second and third boards formed separately from the first board are laminated on the first and second metal foil layers through first and second adhesive layers respectively. Then, a thin layer portion is removed and thick layer portions are formed into predetermined conductor patterns respectively in third and fourth metal foil layers of the second and third boards.Type: ApplicationFiled: April 1, 2002Publication date: October 3, 2002Applicant: NITTO DENKO CORPORATIONInventors: Hiroshi Yamazaki, Mineyoshi Hasegawa, Satoshi Tanigawa